FPGA-based ate test vector compilation acceleration method and ate system

A test vector and basic waveform technology, applied in code compilation, program code conversion, instruments, etc., can solve the problems of long compilation time, affecting compilation time, and compiled software crash, etc., to improve compilation speed, improve compilation efficiency, shorten the The effect of commissioning time

Active Publication Date: 2022-03-18
杭州加速科技有限公司
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] (1) The CPU can only compile each user programming vector one by one according to the structure of the CPU instruction set, and cannot perform large-scale parallel compilation, which has low efficiency and seriously affects the compilation time;
[0006] (2) A large number of table lookup actions required by the CPU to compile the vector process can only be completed in the external memory, and its compilation speed is greatly limited by the memory access bandwidth and delay;
[0007] (3) The CPU compilation vector needs to cache a large amount of intermediate data. When compiling a complex program, it is easy to cause the compilation time to be too long due to insufficient memory and even cause the compilation software to crash.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • FPGA-based ate test vector compilation acceleration method and ate system
  • FPGA-based ate test vector compilation acceleration method and ate system
  • FPGA-based ate test vector compilation acceleration method and ate system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0068] Embodiment 1 of the present invention discloses an FPGA-based ATE test vector compilation acceleration method. The parallel compilation of test vectors is realized through an external FPGA, which greatly improves the compilation efficiency of test vectors. figure 2 As shown, the specific scheme is as follows:

[0069] A method for accelerating the compilation of FPGA-based ATE test vectors is applied in ATE equipment, and the method comprises the following steps:

[0070] 101. The user performs programming based on preset testing machine instructions and predefined basic waveforms, and obtains the Pattern program file in ASCII format;

[0071] 102. Construct the waveform periodic table, edge time table, edge format table and microinstruction table based on the Pattern program file;

[0072] 103. Load the Pattern program file from the CPU of the main control board to the preset accelerated FPGA;

[0073] 104. Accelerate the FPGA to compile the Pattern program file, an...

Embodiment 2

[0096] This embodiment proposes an ATE system, and the ATE system is provided with a compilation acceleration device, which can execute an FPGA-based ATE test vector compilation acceleration method proposed in Embodiment 1. The hardware structure of the ATE system is shown in the attached manual Figure 14 As shown, the specific scheme is as follows:

[0097] An ATE system, comprising a compilation acceleration device 4, a main control board 1, a backplane 2 and at least one service board 3, the backplane 2 is respectively connected to the main control board 1 and the service board 3; the main control board 1 includes a CPU11 and a PCIE interface 5 ; The compilation acceleration device 4 is connected to the main control board 1 through the PCIE interface 5 and establishes a data connection with the CPU 11 . The structure of the ATE system is shown in the attached manual Figure 14 shown.

[0098] An acceleration FPGA is arranged on the compilation acceleration device 4, and...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The present invention proposes an FPGA-based ATE test vector compilation acceleration method and ATE system. The compilation acceleration method includes: writing a Pattern program file according to preset testing machine instructions and basic waveforms; constructing a waveform periodic table, an edge time table, and an edge format table, microinstruction table; download the Pattern program file to the accelerated FPGA. Accelerates FPGA parallel table lookup and records table addresses, and compiles Pattern program files into executable vectors recognizable by the test machine. The invention transfers the execution process of Pattern program compilation to the accelerated FPGA to realize fast compilation of user programs. Compared with the traditional method of compiling test programs by means of the CPU of the main control board, the compilation acceleration scheme of the present invention can not only perform parallel compilation of multiple fields in a single test vector, but also parallel compile multiple test vectors at the same time, greatly Improve the compilation speed of test vectors and greatly shorten the commissioning time of chip testing.

Description

technical field [0001] The invention relates to the field of semiconductor chip testing, in particular to an FPGA-based ATE test vector compilation acceleration method and an ATE system. Background technique [0002] ATE (Automatic Test Equipment) is an automatic test equipment. It is a collection of test instruments controlled by a high-performance computer. It is a test system composed of a tester and a computer. The computer controls the test by running the instructions of the test program. hardware. Semiconductor chip ATE is used to detect the integrity of the function and performance of integrated circuits. It is an important device to ensure the quality of integrated circuits in the manufacturing process of integrated circuits. The test of integrated circuits usually requires test program design, program compilation, vector loading, and testing. Perform four procedures. [0003] Among them, program compilation is the process of compiling the test program and test vec...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/41
CPCG06F8/445
Inventor 陈永邬刚
Owner 杭州加速科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap