31 results about "Vector process" patented technology

A software-accessible special purpose register is architected into a processing unit in order to implement persistent vector multiplexer control of a vector-based execution unit. A persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to be stored in the special purpose register such that the operand vectors processed by subsequent vector instructions executed by the vector-based execution unit will be selectively shuffled using the persisted state information. As a result, when multiple vector instructions require a common custom word ordering for one or more operand vectors, a single persistent swizzle instruction may be used to select the desired custom word ordering for all of the vector instructions.

Persistent vector multiplexer control is used in a vector-based execution unit to control the shuffling of words in operand vectors processed by the execution unit. In addition, a persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to be persisted such that the operand vectors processed by subsequent vector instructions executed by the vector-based execution unit will be selectively shuffled using the persisted state information. As a result, when multiple vector instructions require a common custom word ordering for one or more operand vectors, a single persistent swizzle instruction may be used to select the desired custom word ordering for all of the vector instructions.

The invention relates to a method for concealing time-domain errors on the basis of inter-frame modes and movement repair. The method is mainly technically characterized by comprising steps of classifying processes for concealing the errors according to inter-frame mode information of upper, lower, left and right correct receive blocks adjacent to a current damaged macro block and respectively repairing damaged movement vectors; acquiring reconstruction values of the damaged block in reference frames by the aid of a movement compensation process and repaired movement vectors. The method has the advantages that the inter-frame mode information of the correct receive blocks adjacent to the damaged macro block is sufficiently utilized, the movement vectors of the damaged block are repaired by the aid of the different processes for concealing the errors, the movement compensation process on the basis of sub-blocks is used for complicated areas, a boundary matching process is used for relatively flat areas, a zero movement vector process is used for static areas, accordingly, the movement vectors of the damaged block can be accurately recovered, an error concealment effect is improved, the algorithm complexity is proper, and the instantaneity of the method in mobile application can be guaranteed.

Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the arithmetic unit; and vector processing the data word in the arithmetic unit.

The invention discloses an LDPC linear programming decoding method based on an acceleration alternating direction multiplier method. The LDPC linear programming decoding method mainly solves the problems that an existing message class transmission algorithm has the error floor and can be easily influenced by a short link. According to the technical scheme, the LDPC linear programming decoding method comprises the steps that first, decoding parameters are initialized; second, iteration updating is carried out on an auxiliary vector, a solution vector and a Lagrangian multiplier vector in the decoding parameters in sequence; third, acceleration processing is carried out to correct the solution vector and the Lagrangian multiplier vector; fourth, according to the corrected solution vector, infinite norms of vectors corresponding to all check nodes are calculated, and the maximum infinite norm is worked out; fifth, whether the decoding process ends or not is judged according to the obtained maximum value and the number of times of iteration; sixth, the solution vector processed through the last time of iteration is output to serve as a decoded code word. The LDPC linear programming decoding method is high in convergence rate and free of the error floor, efficiency of a decoding module in a communication system can be remarkably improved, and the LDPC linear programming decoding method is applicable to the technical field of communication.

The invention discloses a program stream control method for a vector processor and a system. The method includes steps of outputting a vector data processing state when a vector data processing unit executes a vector data operation instruction outputted by a fetch unit; acquiring a the vector data processing state by the aid of a program stream control unit; generating a program stream changing mark according to the vector data processing state; starting to sequentially obtain instructions from program stream changing addresses by the aid of the fetch unit according to the program steam changing mark; and outputting acquired instructions to the vector data processing unit. The system comprises the fetch unit, the vector data processing unit and the program stream control unit, the vector data processing unit consists of a state generating unit used for generating the vector data processing state, and an output end of the state generating unit is connected with the program stream control unit. The program stream control method for the vector process and the system have the advantages that a program stream can be changed during processing, vector data processing time is saved, data processing volume is reduced, and data processing efficiency is high.

A data processing apparatus includes a register bank having a plurality of registers for storing vectors being processed; a pipelined processor for processing the stream of vector instructions; the pipelined processor comprising circuitry configured to detect data dependencies for the vectors processed by the stream of vector instructions and stored in the plurality of registers and to determine constraints on timing of execution for the vector instructions such that no register data hazards arise. Register data hazards arise where two accesses to a same register, at least one of said accesses being a write, occur in an order different to an order of said instruction stream such that an access occurring later in said instruction stream starts before an access occurring earlier in said instruction stream has completed. The pipelined processor includes data element hazard determination circuitry.