Three-dimensional quantum chip and preparation method thereof

Abstract

The invention provides a three-dimensional quantum chip, which comprises a quantum bit layer, an auxiliary pattern layer and a wiring layer, wherein the quantum bit layer comprises a first substrate and quantum bits on the first substrate; the auxiliary pattern layer comprises a second substrate, a plurality of auxiliary patterns on the second substrate and a through hole which penetrates through the second substrate and is deposited with metal; the wiring layer comprises a connecting line and a connecting terminal, the first end of the connecting line is connected to the connecting terminal, and the second end of the connecting line is used for outputting data; and the surface, which is provided with the quantum bits, of the quantum bit layer and the surface, which is provided with the auxiliary patterns, of the auxiliary pattern layer are welded together through connecting metal, and the connecting terminal on the wiring layer is connected with the deposited metal in the through hole in the surface of the auxiliary pattern layer without the auxiliary patterns.

Description

technical field [0001] The present invention generally relates to the field of multi-qubit chips, and in particular to a three-dimensional quantum chip and a preparation method thereof. Background technique [0002] The three-dimensional quantum chip is a semiconductor process that uses flip-chip packaging technology to weld two or more chips together upside down. Using this process in the preparation of quantum chips can solve problems such as large crosstalk, difficult integration, and complicated wiring. At present, there are mainly two methods for the preparation of three-dimensional quantum chips. One method is to align the quantum chip with the bit layer with the chip with the wiring layers such as transmission lines, readout chambers, and various control lines through the form of alignment and flipping. Realize a three-dimensional quantum chip (see B.Foxen, et.al.2018Quantum Sci.Technol.3, 014005); another method is to use pins to contact the pins of the leads on the ...

AI Technical Summary

Problems solved by technology

For the first method, wiring for 50-100 qubits can be achieved, but for larger quantities, wiring is very difficult

The larger the number of qubits, the longer the wiring, which greatly reduces the yield during preparation

For the second method, the pins are in contact with the chip, which is likely to cause heat, strain, and easily damage the chip, and the production of the pins is also demanding, including problems such as the force on the pins and the alignment of the pins during contact.

Therefore, using the above method to prepare a chip with hundreds or thousands of qubits not only requires a lot of work but also makes wiring difficult.

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