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Hardware Trojan horse detection method based on LUT behavior analysis

A hardware Trojan detection and behavior analysis technology, applied in the protection of internal/peripheral computer components, instrument, platform integrity maintenance, etc., can solve problems such as difficult hardware Trojan detection, and achieve the effect of solving security risks

Pending Publication Date: 2021-12-07
NORTHWESTERN POLYTECHNICAL UNIV
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AI Technical Summary

Problems solved by technology

Existing detection methods are difficult to detect hardware Trojan horses using external or internal irrelevant items in the integrated circuit design space

Method used

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  • Hardware Trojan horse detection method based on LUT behavior analysis
  • Hardware Trojan horse detection method based on LUT behavior analysis
  • Hardware Trojan horse detection method based on LUT behavior analysis

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specific Embodiment

[0038] Such as figure 2 As shown in the integrated circuit design, the circuit includes 5 sub-modules, wherein sub-module 5 includes a hardware Trojan embedded by an untrusted third-party circuit designer, specifically including Trojan trigger logic and load logic, wherein the Trojan trigger logic is under certain conditions Generate a Trojan horse trigger signal to activate a hardware Trojan horse. After the Trojan horse is activated, the load logic can realize functions such as sensitive information leakage, increased system power consumption, and reduced system performance. In order to improve the concealment of hardware Trojans and prevent them from being detected during the design stage or chip use stage, hardware Trojans are generally activated with a small probability. Specifically, when designing hardware Trojans, the Trojan trigger logic can use counters or specific inputs Vector as Trojan activation condition. In this embodiment, the detected integrated circuit de...

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Abstract

The invention discloses a hardware Trojan horse detection method based on LUT behavior analysis, and the method comprises the following steps: inputting a design code of a detected integrated circuit in the form of a register transfer-level code or a gate-level netlist, and then synthesizing the design of the integrated circuit into a netlist realized based on an FPGA based on a synthesis tool; then, at different simulation times, carrying out the random input function simulation on the generated FPGA netlist, and storing the signal behavior lists at different simulation times; analyzing the signal behavior list to obtain a low-upset-rate signal list at different simulation times; finally, based on the signal behavior list and the FPGA netlist, performing LUT address line coverage rate analysis to obtain a low-coverage-rate LUT list; and when the low flipping rate signal list and the low coverage rate LUT list converge to a fixed set, determining a hardware Trojan trigger signal and trigger logic in the detected integrated circuit design. The method can solve potential safety hazards in the early stage of integrated circuit design, and has unique advantages in the aspect of irrelevant item Trojan horse detection.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a hardware Trojan horse detection method. Background technique [0002] With the increase of integrated circuit design scale, system-on-chip (SoC, System-on-Chip) design usually uses a large number of intellectual property (IP, Intellectual Property) cores provided by untrusted third parties to improve product development speed. Reduce design cost. Malicious design modifications and backdoors that are not disclosed outside the design specification may be hidden in these IP cores. Malicious design modifications in integrated circuit designs introduced by untrusted third parties are called hardware Trojans. Hardware Trojans are usually activated only under specific conditions, and it is difficult to detect hardware Trojans based on integrated circuit functional testing methods. Attackers can activate the Trojan horse through specific input vectors, side c...

Claims

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Application Information

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IPC IPC(8): G06F21/56G06F21/55G06F21/76
CPCG06F21/566G06F21/556G06F21/76
Inventor 胡伟武玲娟邰瑜
Owner NORTHWESTERN POLYTECHNICAL UNIV
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