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Semiconductor device and its preparation method

A technology for semiconductors and devices, applied in the field of semiconductor devices and their preparation, can solve problems such as increased ground resistance of back metal, deformation of front source metal, device failure, etc., to avoid resistance increase, ensure integrity, and ensure reliability. Effect

Active Publication Date: 2022-02-25
深圳市时代速信科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In the prior art, the through hole on the back of the chip and the back surface only cover the back metal layer. During soldering or device use, the solder metal will enter the through hole and diffuse through the back metal layer to the front of the chip, resulting in front source Deformation or damage of pole metals, leading to device failure
At the same time, the solder and the back metal are in direct contact with each other, resulting in an increase in the grounding resistance of the back metal

Method used

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  • Semiconductor device and its preparation method
  • Semiconductor device and its preparation method
  • Semiconductor device and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0063] see figure 1 with figure 2 , this embodiment provides a semiconductor device 100, which can prevent solder from intruding into the back through hole 131 and the front metal, improve the integrity of the back metal, and avoid the increase of the grounding resistance caused by the mutual dissolution of the solder metal and the back metal.

[0064] The semiconductor device 100 provided in this embodiment includes a wafer body 110, a conductive metal layer 130, a back gold conductive layer 150, and a metal shielding layer 170. The wafer body 110 has opposite first and second surfaces, and the conductive metal layer 130 Set on the first surface of the wafer body 110, the second surface of the wafer body 110 is etched to form a through hole 131, the through hole 131 penetrates through the wafer body 110 to the conductive metal layer 130, and the back gold conductive layer 150 is arranged on The second surface of the wafer body 110 is also arranged on the sidewall of the thr...

no. 2 example

[0079] see image 3 , this embodiment provides a semiconductor device 100, the basic structure and principle and the technical effect produced are the same as those of the first embodiment. For a brief description, the part not mentioned in this embodiment can refer to Corresponding content.

[0080] In this embodiment, the semiconductor device 100 includes a wafer body 110, a conductive metal layer 130, a back gold conductive layer 150 and a metal shielding layer 170, the wafer body 110 has opposite first and second surfaces, and the conductive metal layer 130 Set on the first surface of the wafer body 110, the second surface of the wafer body 110 is etched to form a through hole 131, the through hole 131 penetrates through the wafer body 110 to the conductive metal layer 130, and the back gold conductive layer 150 is arranged on The second surface of the wafer body 110 is also arranged on the sidewall of the through hole 131 and is electrically connected to the conductive m...

no. 3 example

[0086] see Figure 4 , this embodiment provides a semiconductor device 100, the basic structure and principle and the technical effect produced are the same as those of the first embodiment or the second embodiment. The corresponding content in the first embodiment or the second embodiment.

[0087] In this embodiment, the surface of the metal shielding layer 170 is further provided with a first solder resist layer 180 , and the first solder resist layer 180 is filled in the liquid guide hole 171 for blocking solder.

[0088] In this embodiment, the side of the metal shielding layer 170 away from the conductive metal layer 130 is provided with a groove 175 corresponding to the through hole 131, the liquid guide hole 171 is located in the groove 175, and the groove 175 is on the first surface. The projection size is smaller than the projection size of the opening of the through hole 131 on the first surface, the first solder resist layer 180 is arranged in the groove 175 and t...

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Abstract

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technology. The semiconductor device includes a wafer body, a conductive metal layer, a back gold conductive layer and a metal shielding layer. By setting the metal shielding layer, and The opening of the through hole forms a shielding structure, which can effectively prevent the solder from entering the inside of the through hole when the chip is soldered or used, and also prevents the solder from diffusing through the back gold conductive layer to reach the first surface, ensuring the integrity of the back gold conductive layer. Integrity, thereby ensuring the reliability of the device. At the same time, the present invention avoids solder erosion of the back gold conductive layer on the side wall of the through hole, thereby avoiding the phenomenon of increased resistance caused by the mutual dissolution of the solder and the back gold conductive layer, and also avoiding the large difference in thermal expansion coefficient between the solder and the side wall of the through hole The resulting problem of poor mechanical properties of the chip.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background technique [0002] For RF power devices, the source ground is usually achieved using back hole technology. Backside vias penetrate the substrate and semiconductor layers from the backside of the chip to under the source metal on the front side of the chip. The source metal on the front side of the chip is connected to the metal on the back side by covering the bottom, sidewall and backside surface of the through hole with metal. When the chip is packaged, the metal (Au) on the back of the chip, the solder (AuSn), and the frame are stacked together, and bonded together at a certain temperature to realize the grounding of the chip source. [0003] In the prior art, the through hole on the back of the chip and the back surface only cover the back metal layer. During soldering or device use, the solder metal...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/48H01L23/488H01L21/768H01L21/60
CPCH01L23/481H01L21/76898H01L24/05H01L24/03H01L2224/05005H01L2224/05009H01L2224/0501H01L2224/05025
Inventor 杨天应刘丽娟吴文垚
Owner 深圳市时代速信科技有限公司