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Semiconductor structure and preparation method thereof

A technology of semiconductor and alignment direction, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc. The effect of optimizing engraving process conditions, ensuring alignment accuracy, and simplifying complexity

Pending Publication Date: 2021-12-17
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The quality of the alignment marks affects the alignment accuracy of the photolithography process, and the alignment marks in the prior art have problems of poor quality

Method used

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in each embodiment of the present invention, many technical details are provided for readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can also be realized.

[0033] refer to figure 1 , the semiconductor structure includes: a substrate 100; a first mask layer (not marked) on the substrate 100, the first mask layer has a plurality of discrete first mask patterns 101; A second mask layer (not shown), the second mask layer has a second mask pattern 102 , at least part of the sidewall of the second mask pattern 10...

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Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a first mask layer, wherein the first mask layer is located on the substrate, and the first mask layer is provided with a plurality of discrete first mask patterns; and a second mask layer, wherein the second mask layer is located on the first mask layer, the second mask layer is provided with a second mask pattern, and at least part of the side wall of the second mask pattern is located at the top of the first mask pattern. According to the invention, the alignment precision of the photolithography process can be improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] With the development of the integrated circuit manufacturing process, the feature size of the lithography process is getting smaller and smaller. In order to ensure the quality of the lithography process, the alignment system of the lithography machine needs to check the photomask and the wafer before performing lithography. alignment between. Generally speaking, the lithography alignment system measures multiple alignment marks on the wafer, positions the alignment marks, and calculates the exact position during exposure to achieve extremely small overlay errors. [0003] The quality of the alignment marks affects the alignment accuracy of the photolithography process, and the alignment marks in the prior art have the problem of poor quality. Contents of the inve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L21/027H01L21/033
CPCH01L23/544H01L21/0271H01L21/0332H01L21/0337H01L2223/54426H01L29/66227
Inventor 张胜安黄仁洲
Owner CHANGXIN MEMORY TECH INC