Semiconductor packaging structure

Abstract

The invention provides a semiconductor packaging structure. Discrete components are integrated in advance to form a stacked passive component integrated body, and the stacked passive component integrated body can provide a signal transmission path in the Z-axis direction, so that the internal signal transmission path between the discrete components can be shortened, and the signal transmission loss between the discrete components can be reduced. In addition, when dielectric material lamination is carried out after the stacked passive component integrated body is embedded in the substrate, the generation of holes can be avoided, and the productivity and the yield are improved.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, and in particular to semiconductor packaging structures. Background technique [0002] Figure 1-Figure 3 shows the method of integrating passive components, first refer to figure 1 , provide a substrate 1 with a cavity 101, then refer to figure 2 , using a pick-up device to embed a plurality of passive components 2 into the cavity 101, and finally refer to image 3 After laminating the dielectric material 3, via holes are formed by laser and the circuit layer 4 is formed by electroplating. [0003] However, with the above method, the embedded passive components are integrated in a planar arrangement, resulting in an increase in the dimension in the X-Y plane direction. In addition, the connection path between the passive components 2 is relatively long, resulting in relatively large signal loss. When the passive components 2 are picked and placed multiple times, the spacing...

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Problems solved by technology

[0003] However, with the above method, the planar placement method integrates embedded passive components, resulting in an increase in the size of the X-Y plane direction

In addition, the connection path between passive components 2 is longer, resulting in greater signal loss

When picking and placing the passive components 2 for many times, the spacing between the passive components 2 is inconsistent due to the error of the picking and placing process. When the spacing is small, the dielectric material 3 is not easy to press, and the dielectric material 3 is prone to voids (void)

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