Bare chip and manufacturing method thereof, and chip packaging structure and manufacturing method thereof
A technology of chip packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems affecting product performance, restricting product miniaturization, etc., and achieve the effect of improving yield and reducing resistance
Pending Publication Date: 2022-01-28
SIPLP MICROELECTRONICS CHONGQING CO LTD
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Problems solved by technology
Packaging technology not only restricts the miniaturization of products, but also affects the performance of products
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[0053] In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0054] figure 1 It is a flowchart of a method for manufacturing a bare chip according to the first embodiment of the present invention. Figure 2 to Figure 4 Yes figure 1 The schematic diagram of the intermediate structure corresponding to the process in ; Figure 5 It is a schematic cross-sectional structure diagram of the bare chip according to the first embodiment of the present invention.
[0055] First, refer to figure 1 in step S1, figure 2 and image 3 shown, figure 2 is the top view of the wafer, image 3 is along the figure 2 The cross-sectional view of the AA line in the middle, provides a wafer 11, the wafer 11 includes a passivation layer 111 and a plurality of aluminum pads 112, the passivation layer 111 and t...
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Abstract
The invention provides a bare chip, a manufacturing method of the bare chip, a chip packaging structure and a manufacturing method of the chip packaging structure. The bare chip comprises an aluminum welding pad, a passivation layer and a copper layer. The aluminum bonding pad and the passivation layer are located on the active surface of the bare chip, the passivation layer is provided with an opening, and the opening exposes a partial region of the aluminum bonding pad; and the copper layer is filled in the opening of the passivation layer and covers the surface of the aluminum bonding pad. The copper layer is formed on the aluminum bonding pad, and the copper layer is filled in the opening of the passivation layer, so that on one hand, the copper layer can prevent the surface of the aluminum bonding pad from being oxidized, and the resistance of the aluminum bonding pad is reduced; secondly, when a hole is formed in the plastic packaging layer by adopting a laser hole opening method, the copper layer can prevent the aluminum welding pad from being punctured due to excessive laser energy; and in the third aspect, the copper layer is completely located in the opening of the passivation layer, and relative to the scheme that the copper layer is partially located on the passivation layer, the copper layer can be prevented from being stripped from the passivation layer due to poor bonding performance of the copper layer and the passivation layer, so that the yield of the packaging structure is improved.
Description
technical field [0001] The invention relates to the technical field of chip packaging, and in particular, to a bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof. Background technique [0002] In recent years, with the continuous development of circuit integration technology, electronic products are developing in the direction of miniaturization, intelligence, high integration, high performance and high reliability. Packaging technology not only restricts product miniaturization, but also affects product performance. [0003] In view of this, the present invention provides a new bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing method thereof, so as to improve the yield of the packaging structure. SUMMARY OF THE INVENTION [0004] The purpose of the present invention is to provide a bare chip and a manufacturing method thereof, a chip packaging structure and a manufacturing...
Claims
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IPC IPC(8): H01L23/538H01L21/768
CPCH01L23/5386H01L21/76895
Inventor 霍炎杨威源杨磊
Owner SIPLP MICROELECTRONICS CHONGQING CO LTD