UVM-based transponder chip multi-module synchronous verification platform and verification method

Abstract

The invention discloses a UVM-based transponder chip multi-module synchronous verification platform and verification method. Linkage among a plurality of modules in the working process of the transponder chip is considered; a code writing module, a code reading module and an active module of the transponder chip are simultaneously instantiated into a to-be-tested design DUT for simulation verification; the mutual cooperation operation relation between modules of the transponder chip is better met, and simulation closer to the actual environment can be achieved. The three modules are verified as a whole; compared with verification by a single module, part of external interfaces are changed into internal interface signals, and the number of interface excitation needing to be applied is reduced; meanwhile, signal matching between the modules is closer, and matching output of one module to the other module is needed; during debugging, signals need to be observed in a combined manner, and the coordination and consistent work of the three modules of the transponder is embodied. Functional modules in a plurality of transponder chips can be verified at the same time, and the verification efficiency of the transponder chips can be improved.

Description

technical field [0001] The invention belongs to the field of chip verification, in particular to a UVM-based transponder chip multi-module synchronous verification platform and verification method. Background technique [0002] Existing transponder chips do not involve verification of transponder modules using the UVM verification platform. In the past, the simulation verification platform for transponder chips was based on simple Verilog code, which applied simple stimulus to the input and output ports, and there was no systematic and modular way to verify the transponder chip in all directions, which led to the Many bugs were not discovered in time. [0003] With the continuous development of the integrated circuit industry, the complexity of the design part of the chip is increasing, and the scale of the chip is increasing proportionally, which brings difficulties to the verification. The chip needs to be successfully taped out after repeated tape-out failures. Improvin...

AI Technical Summary

Problems solved by technology

This verification method can reduce the development cost of large-scale system design and quickly simulate the logic capability of the design. However, the signal visibility of the FPGA prototype system verification is poor, and it is difficult to verify the extreme boundary under normal conditions. It can only be carried out under special circumstances. It is generally suitable for stable post-system design integration verification, and not suitable for functional verification in the early stage of chip development.

[0006] The transponder chip usually contains multiple functional modules, and the overall linkage of the transponder is usually the result of the linkage of multiple modules. The common verification platform is to verify each functional module one by one, which is not only inefficient, but also unable to simulate the response practical application scenarios

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