Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate, enabling a gate structure to be arranged on the substrate, enabling source-drain doping layers to be arranged in the substrate at two sides of the gate structure, enabling a first dielectric layer to be arranged on the substrate exposed out of the gate structure, and enabling the substrate to comprise a plurality of adjacent device unit regions in the extension direction of the gate structure; forming a barrier layer at the top of the first dielectric layer at the junction of the device unit regions; etching partial thickness of the first dielectric layer by taking the barrier layer as a mask, and forming an opening for exposing the top of the source-drain doping layer in the first dielectric layer on two sides of the gate structure; forming a bottom source-drain plug at the top of the source-drain doping layer exposed from the opening; forming a second dielectric layer on the top of the bottom source drain plug, wherein the second dielectric layer covers the side wall of the barrier layer; and forming a top source-drain plug electrically connected with the bottom source-drain plug in the second dielectric layer, wherein the top source-drain plugs in the adjacent device unit regions are isolated through a barrier layer. According to the invention, the alignment precision of the top source-drain plug and the corresponding bottom source-drain plug is improved through the barrier layer.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The inte...

AI Technical Summary

Problems solved by technology

In order to improve integration and reduce costs, the critical dimensions of components are continuously reduced, and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines.

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