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Manufacturing method of semiconductor device

A manufacturing method and semiconductor technology, which can be used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve problems such as reduced carrier mobility and uneven distribution of doped layers.

Pending Publication Date: 2022-03-01
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the use of ion implantation in the lightly doped drain doped region will make the distribution of the doped layer in the doped region uneven, resulting in a decrease in carrier mobility, which does not prevent or suppress the shortening of the conductive channel length. The effect of causing leakage current between source and drain

Method used

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  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device

Examples

Experimental program
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Embodiment 1

[0029] The manufacturing method of a kind of preferred embodiment semiconductor device of the present invention, comprises the following steps:

[0030] In step S1, the process before ion implantation into the doped region of the lightly doped drain is completed.

[0031] Specifically, the process steps can be as follows:

[0032] Firstly, a semiconductor substrate 10 is provided. The semiconductor device has a first direction and a second direction. The substrate 10 may be a wafer, such as a silicon wafer. In some embodiments, the semiconductor material of substrate 10 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or combinations thereof .

[0033] Then, the sti can be formed by a photolithography process, and then the photoresist is removed, and then the groove is etched, and a pad oxide layer is grown; after that, the fin 50 can be forme...

Embodiment 2

[0043] The difference between the second embodiment and the first embodiment is that the semiconductor device in the second embodiment is a nanosheet transistor, and the doping layer is formed in the source region and the drain region of the nanosheet transistor.

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Abstract

The invention discloses a method for manufacturing a semiconductor device, which comprises the following steps of: S1, finishing a process before ion implantation into a lightly doped drain doped region, and forming a device comprising a dummy gate structure formed on the surface of a semiconductor; the semiconductor device has a first direction and a second direction, and a source region and a drain region are formed on two sides of the second direction of the semiconductor device; s2, depositing a doping layer and annealing; and S3, removing the redundant doping layer. According to the invention, the doped layer of the doped region is uniformly distributed, so that the carrier mobility is improved, the leakage current between the source electrode and the drain electrode caused by the shortening of the length of the conductive channel is avoided or inhibited, and the performance of the transistor is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the continuous improvement of the integration level of semiconductor devices, the feature size is gradually reduced, and the challenges from manufacturing and design have prompted the development of three-dimensionally designed transistors. Examples include fin field effect transistors (FinFETs) and nanosheet transistors (nanosheet). [0003] Compared with the existing planar transistors, FinFET is an advanced semiconductor device for 20nm and below process nodes, including a Fin perpendicular to the bulk silicon substrate. The source region, drain region and channel region are defined inside, and different FinTETs are separated by the STI structure. The gate stack formed by the gate insulating layer and the gate layer surrounds Fin on the side and the top surface, so that the F...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/10H01L29/78
CPCH01L29/1033H01L29/785H01L29/66795
Inventor 翁文寅
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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