Analog-to-digital conversion method of pipelined ADC

Abstract

The invention discloses an analog-to-digital conversion method for a pipelined ADC, and the method comprises the following steps: S100, carrying out the sampling and holding of an analog input signal through a sampling and holding circuit, and transmitting the analog input signal to a sub-ADC and a dynamic amplifier; s200, the sub-ADC quantizes the analog input signal and outputs a quantization result to an output register for latching; s300, after the dynamic amplifier amplifies the analog input signal, the analog input signal is transmitted to a residual error generation circuit; s400, the sub-DAC generates a quantization feedback signal according to the quantization result of the sub-ADC, and transmits the quantization feedback signal to the residual error generation circuit; s500, a residual error generation circuit subtracts the amplified analog input signal from the quantized feedback signal to obtain a residual error signal; and S600, the next stage of assembly line unit receives the residual error signal, and the steps S100 to S500 are repeated until the last stage of assembly line unit completes the action. According to the analog-to-digital conversion method of the pipelined ADC, the quantification process and the amplification process of the pipelined unit are decoupled, and the operation speed of the whole system is improved.

Description

technical field [0001] The invention relates to the technical field of analog-to-digital converters, in particular to an analog-to-digital conversion method of a pipelined ADC. Background technique [0002] Direct RF sampling (Direct RF sampling) technology provides a lot of convenience for broadband and multi-band communication, but it puts forward extremely high performance requirements for the required analog-to-digital converter (ADC), requiring that its input bandwidth and sampling rate are not low In gigahertz. Time-interleaving (time-interleaving) technology, as an important technology of gigahertz RF sampling analog-to-digital converters, can effectively increase the sampling rate of the system, but a large number of time-interleaving channels will significantly increase the system complexity and introduce various mismatch errors. This in turn reduces system performance and stability. In a time-interleaved ADC system, increasing the sampling rate of a single-channe...

AI Technical Summary

Problems solved by technology

Therefore, the conversion rate of the pipeline ADC is limited by the time required for the single-stage pipeline to sequentially complete sampling, quantization, and residual amplification

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