Planar power semiconductor device

Abstract

The invention discloses a planar power semiconductor device. A device unit comprises a first epitaxial layer formed on a substrate; the gate structure is formed on the surface of the first epitaxial layer; the source region and the first side surface of the gate structure are self-aligned; a gap is formed between the drain region and the second side surface of the gate structure; the drift region is located between the second side surface of the gate structure and the drain region; the conductive channel is composed of an inversion layer formed during inversion of the surface of the first epitaxial layer covered by the gate structure; the doping concentration distribution of the drift region forms a charge balance structure, and during reverse biasing, the charge balance structure enables the drift region to be completely exhausted and the surface electric field to be uniformly distributed. The charge balance structure of the drift region can be realized, so that the specific on-resistance can be reduced, the energy loss of the device when the device is turned on is greatly reduced, the method is particularly suitable for a gallium nitride power device, the advantages of a gallium nitride material can be fully played, the manufacturing cost of the gallium nitride device is reduced, and the technological process is simplified.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a planar power semiconductor device. Background technique [0002] The specific on-resistance (Ron, sp) of existing power devices is related to the breakdown voltage (Breakdown Voltage), and a higher breakdown voltage often results in a relatively high specific on-resistance. For traditional power semiconductor devices, there is a physical limit of Ron,sp vs. BV, also known as the one-dimensional physical limit (1-D limit). The invention of charge power devices can break this limit. The most typical charge balance device structure is the superjunction device. Conventional superjunction devices use different doping (N-type and P-type doping) in the drift region to form a charge balance structure. This superjunction process is relatively mature in silicon devices, but cannot be applied to wide-bandgap semiconductors. Especially in gallium nitride, d...

AI Technical Summary

Problems solved by technology

This super junction process is relatively mature in silicon devices, but it cannot be applied to wide bandgap semiconductors

Images