I3C bus verification method and verification system

Abstract

The invention discloses an I3C bus verification method, which is realized on the basis of a UVM platform and comprises the following steps of: a, establishing a verification platform through the UVM, and constructing components of a top layer, a middle layer and a bottom layer; b, compiling a test case of a single test so as to be matched with a to-be-tested design; and c, running the test case through the EDA tool to carry out verification test, and obtaining a verification result. Meanwhile, the invention further discloses an I3C bus verification system applied to the I3C bus verification method. According to the scheme of the invention, a verification engineer can flexibly change the attribute of the verification platform according to a specific design specification, and the integrity and high efficiency of verification are ensured.

Description

technical field [0001] The invention relates to the field of digital verification, and more particularly to an I3C bus verification method and verification system. Background technique [0002] At present, with the increasing integration and complexity of chips, it is a great challenge to verify the design under test more completely and efficiently. The I3C bus standard adds new functions on the basis of the I2C bus standard, such as dynamic address allocation, in-band interrupts, etc., and provides higher data rates and is compatible with I2C devices, so it is necessary to verify the integrated I3C bus completely and efficiently. The design of the protocol is more difficult than the verification of the traditional I2C bus protocol, because the verification of the I2C bus already has mature verification IP, and for the verification of the I3C bus protocol, the existing technology is through FPGA (Field Programmable Gate Array). ) or other fixed equipment simulates I3C equip...

AI Technical Summary

Problems solved by technology

[0003] However, the above-mentioned existing technologies use FPGA or fixed I3C devices to communicate with the design to be tested, but at present the demand for chips in various industries is particularly large, and there are various types of sensors or other communication devices in various fields, relying on fixed It is difficult to verify the use of I3C bus in various fields, lack of randomness of verification, and the cost of a large number of I3C devices is difficult to estimate

If FPGA is used to simulate I3C devices for verification, code replacement according to different situations will be very cumbersome and error-prone

In addition, relying on a fixed I3C device or an FPGA to simulate an I3C device can usually only verify normal communication with the design under test. The lack of randomness testing can easily cause the verification engineer to miss the bus communication under abnormal conditions, and these abnormal conditions that are easily overlooked are due to The probability of triggering is small, and it is almost impossible to be found in the normal test process, but if it happens to the actual chip finished product, the consequences may often be fatal. Therefore, it is necessary to provide an improved I3C bus verification method and verification system to overcome the above defects

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