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Semiconductor gate structure and preparation method thereof

A gate structure and semiconductor technology, which is applied in the direction of semiconductor devices, transistors, electrical components, etc., can solve the problems of small selection of metal filling process, etc., and achieve the effect of reducing the difficulty of metal deposition, reducing resistance, and wide application range

Pending Publication Date: 2022-07-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The second object of the present invention is to provide a method for preparing the above-mentioned semiconductor gate structure, which can obtain amorphous metal nitride by using ALD or PEALD method, thereby solving the problem of small selection of metal filling process

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  • Semiconductor gate structure and preparation method thereof
  • Semiconductor gate structure and preparation method thereof

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Embodiment Construction

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and those skilled in the art will Regions / layers with differen...

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Abstract

The invention relates to a semiconductor gate structure and a preparation method thereof. The semiconductor gate structure comprises a semiconductor substrate, the semiconductor substrate is provided with a gate trench, and a dielectric layer, a barrier layer and a metal layer are sequentially deposited in the gate trench; wherein the barrier layer is an amorphous metal nitride. The invention discloses a preparation method of a semiconductor gate structure. The preparation method comprises the following steps: etching a gate trench on a semiconductor substrate; depositing a dielectric layer on the bottom wall and the side wall of the gate trench; depositing a barrier layer on the bottom wall and the side wall of the gate trench by adopting an ALD or PEALD method, and forming the barrier layer on the surface of the dielectric layer; the barrier layer is an amorphous metal nitride; and then filling metal in the gate trench. According to the invention, the amorphous metal nitride is used as the barrier layer, so that the barrier layer is thinner and occupies smaller space, more space and more free process space are reserved for metal filling, and the difficulty of the metal filling process is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a semiconductor gate structure and a preparation method thereof. Background technique [0002] Dynamic random access memory (Dynamic Random Access Memory, DRAM for short), as a well-known semiconductor storage device, is currently widely used in various electronic devices. Dynamic random access memory (DRAM) is composed of many repeated memory cells (cells). The cells are electrically connected to each other through a word line (WL for short) and a bit line (BL) for short. [0003] In order to improve the integration level of dynamic random access memory (DRAM) and speed up the operation speed of components, as well as to meet the needs of consumers for miniaturized electronic devices, the design of the transistor channel area in DRAM recently has a continuous trend of shortening, but so As a result, the transistor will have serious short channel effect and on current drop....

Claims

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Application Information

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IPC IPC(8): H01L29/423H01L21/28H01L27/108
CPCH01L29/4236H01L29/42364H01L21/28008H10B12/00
Inventor 金玄永郭挑远徐康元高建峰项金娟杨涛李俊峰王文武
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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