High gain detector techniques for low bandwidth low noise phase locked loops

Abstract

The invention relates to high gain detector techniques for low bandwidth low noise phase locked loops. In described examples, a feedback loop has phase detection (PD) circuitry (2412) having a reference input for receiving a reference frequency signal, a feedback input for receiving a feedback signal, and a phase difference output. A phase-to-digital converter (P2DC) (Fig. 24) includes: a first phase-to-charge converter (PCC) (2425) having a gain polarity and a first phase error output; a second PCC (2426) having an opposite gain polarity and a second phase error output. The differential loop filter (2401) has an amplifier (2420) having an inverting input (2421) coupled to the first phase error output and a non-inverting input (2422) coupled to the second phase error output. An analog-to-digital converter (ADC) (2431) has an input coupled to the output of the differential loop filter. A feedback path is coupled to the output of the P2DC, the output of the feedback path providing a feedback signal to the PD feedback input.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 136,245, filed January 12, 2021, the entirety of which is incorporated herein by reference. technical field [0003] This application relates to high gain phase detector techniques for low noise feedback loops. Background technique [0004] Low phase noise operation of a phase locked loop (PLL) or correlated feedback structure is achieved through high gain phase detector (PD) technology. High-gain PDs allow for low detector noise, which is often a critical bottleneck for low phase noise at low frequency offsets. [0005] There are several techniques for implementing high gain PD functionality. An example is a slope-based sampling PD structure, see for example: “A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly LinearDTC Incorporating Background DTC Gain Calibration and Reference Clock DutyCycle Correction,” Wanghua Wu et al, 2...

AI Technical Summary

Problems solved by technology

The slope-based sampling PD structure provides high gain, but suffers from process and temperature (PT) sensitivity of this gain since the slope will typically be affected by PT variations

Up / Dn RC charging circuits provide gain that is generally robust to PT variations, but is generally more limited by supply voltage than slope-based structures

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