Process for preparing MOS transistor

Abstract

A metal oxide semiconductor transistor manufacturing process is to sequentially form a gate dielectric layer and a polysilicon layer on a substrate, and then implant nitrogen ions into the contact area between the polysilicon layer and the gate dielectric layer. Next, a tempering step is performed to make the polysilicon grains in the polysilicon layer larger, and then the polysilicon layer is patterned to form a gate, and doping impurities are implanted into the substrate on both sides of the gate to form a source / drain pole.

Description

technical field [0001] The invention relates to a semiconductor process, and in particular to a manufacturing process of a metal oxide semiconductor transistor (MOS Transistor). Background technique [0002] The known MOS process is to sequentially form a gate oxide layer and a polysilicon layer on a substrate, and then perform a tempering step to make the polysilicon grains in the polysilicon layer larger, then pattern the polysilicon layer to form a gate, and then Doping impurities are doped into the substrate on both sides of the gate to form source / drain. [0003] However, during the tempering process of the known MOS process, the polysilicon located near the newly grown grain boundary (Grain Boundary) will react with the gate oxide layer to generate volatile SiO, which will consume the gate near the grain boundary. Oxide layer, resulting in uneven thickness of the entire gate oxide layer. [0004] When the degree of component integration gradually increases, the thick...

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Problems solved by technology

If the thickness variation of the gate oxide layer in the above tempering process is about 6 Å to 10 Å, when the thickness of the gate oxide layer is 100 Å, the thickness change rate of the gate oxide layer is only about 10%. , the element still has sufficient stability at this time; however, when the thickness of the gate oxide layer drops to 25 Å, the thickness change rate of the gate oxide layer increases to about 50%, which will cause considerable damage to the stability of the element. big impact

[0005] In addition, during the tempering process of the known method, the dopant impurities located in the gate are easily diffused into the underlying substrate due to the double influence of high temperature and polysilicon grain size, thereby changing the electrical characteristics of the element, and May cause component failure and reduce product yield

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