Non-volatile memory and method for manufacturing same

Abstract

A non-volatile memory and its manufacturing method provide a substrate with a storage unit area and a peripheral element area. Then, an electron trapping layer covering at least part of the memory cell area and a first gate layer covering at least the electron trapping layer are sequentially formed on the substrate. Next, after forming at least a gate oxide layer and a second gate layer in the peripheral device area, the first gate layer is patterned to form a plurality of memory gates. The non-volatile memory and its manufacturing method can reduce damage to the electron trapping layer, and reduce the exposure of the storage unit to the thermal environment in the CMOS process.

Description

technical field [0001] The present invention relates to a semiconductor memory element, and more particularly to a nonvolatile memory and a manufacturing method thereof. Background technique [0002] In the manufacturing process of the non-volatile memory, the electron trap layer (Electron Trap Layer) including silicon oxide / silicon nitride / silicon oxide (Oxide / Nitride / Oxide, ONO) is easily damaged when forming peripheral elements. Generally speaking, if the non-volatile memory memory cells and the ONO layer are formed after the Complementary Metal-Oxide Semiconductor (CMOS) process of the peripheral components, the exposed memory cells will be damaged due to the thermal process. . Moreover, the thermal cycle in the CMOS process will also cause impurity diffusion in the buried bit line (Buried Bit Line), which limits the ability of the manufacturer to reduce the feature size (Feature Size) of the device. Contents of the invention [0003] In view of this, the object of t...

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Problems solved by technology

Generally speaking, if the non-volatile memory memory cells and the ONO layer are formed after the Complementary Metal-Oxide Semiconductor (CMOS) process of the peripheral components, the exposed memory cells will be damaged due to the thermal process.

Moreover, the thermal cycle in the CMOS process will also cause the diffusion of impurities in the buried bit line (Buried Bit Line), which limits the ability of the manufacturer to reduce the feature size of the device (Feature Size)

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