Destructive-read random access memory system buffered with destructive-read memory cache

Abstract

A memory storage system (10) is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks (12) and a cache (14) in communication therewith. Both the plurality of memory storage banks (12) and the cache (14) further include destructive read memory storage elements.

Description

Technical field [0001] The present invention generally relates to integrated circuit memory devices, and more particularly to a random access memory system for destructive-read memory caches of destructive-read memory. Background technique [0002] The development of sub-micron CMOS technology has contributed to a significant increase in microprocessor speed. (Increase speed) About four times every three years, the microprocessor speed has exceeded 1Ghz. Together with these advances in microprocessor technology, more advanced software and multimedia applications have been brought, which subsequently require larger memories for the applications therein. Therefore, there is an increasing demand for larger dynamic random access memories (DRAM) with higher density and performance. [0003] In these years, driven by the demands of systems requiring greater memory capacity, DRAM structures have been developed. However, the speed of DRAM characterized by its random access time (tRAC) an...

AI Technical Summary

Problems solved by technology

While such approaches are effective for reducing random access cycle times, the use of SRAM-based caches can take up an undesired amount of chip real estate and result in more costly resources for transferring data between DRAM and cache. complex interconnection

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