Semiconductor package device with layer-increasing structure and making method thereof

Abstract

The capsulation piece comprises following parts: hard base, hard frame possessing through hole fixed on the hard base, at least one chip accommodated in the through hole of hard frame, medium filled in gap between chip and hard frame, addition layer structure formed on the chip and hard frame and connected to the chip electrically, multiple pieces of conducting subassemblies soldered on addition layer in use for connecting the chip to external devices electrically. Since the hard base and hard frame are adopted, the disclosed capsulation piece can prevent problems of structural warp, fragmentation, delamination and gas explosion etc. from happening. The invention discloses method for preparing the capsulation piece of semiconductor in wafer level further.

Description

technical field [0001] The present invention relates to a wafer-level semiconductor package and its manufacturing method, in particular to a build-up structure formed on the Active Surface of the chip, so that the exposed contacts (External Contacts) for solder ball implantation A wafer-level semiconductor package extending out of the active surface of the chip and its manufacturing method. Background technique [0002] In order to meet the requirements of thin, light and small electronic products, semiconductor packages, which are the core components of electronic products, are also developing in the direction of miniaturization. One form of miniaturized semiconductor package developed in the industry is chip scale package (Chip Scale Package, CSP), which is characterized in that the size of the chip scale package is equal to the size of the chip or about 1.2 larger than the size of the chip times. [0003] Furthermore, in addition to miniaturization in size, the semicond...

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Problems solved by technology

[0008] The U.S. Patent No. 6,498,387 uses a glass plate 71 as the carrier of the chip 70. The hard property of the glass plate 71 can solve the problem of warping and cracking of the colloid in the No. 6,271,469 patent, and because the glass plate 71 and The CTE of the chip 70 is similar, so there is no delamination problem caused by the above-mentioned CTE difference; however, the chip 70 is completely covered by the epoxy resin layer 72, often due to the thermal expansion coefficient of the chip 70 and the epoxy resin layer 72 The difference (CTE Mismatch) in the temperature cycle of the subsequent process will cause the chip 70 to be affected by the thermal stress and crack

At the same time, the side 720 of the epoxy resin layer 72 is directly exposed to the atmosphere, that is, due to the high hygroscopicity of the epoxy resin itself, the external moisture will accumulate on the active surface of the chip 70 through the epoxy resin layer 72, so It will cause the problem of popcorn, which will further prevent the reliability of the finished product from being improved

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