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Semiconductor storage apparatus containing image RAM

A storage device and semiconductor technology, applied in the field of image RAM, can solve problems such as high-capacity structural barriers of storage capacitors

Inactive Publication Date: 2003-04-16
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

It also creates obstacles in obtaining a high-capacity structure of storage capacitors similar to the above-mentioned conventional type video RAM

Method used

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  • Semiconductor storage apparatus containing image RAM
  • Semiconductor storage apparatus containing image RAM
  • Semiconductor storage apparatus containing image RAM

Examples

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Embodiment Construction

[0044] Next, embodiments of the present invention are explained with reference to the drawings. 2A to 4C show an example of applying the present invention to an SRAM of a four-layer structure described in the conventional art. In addition, the cross-sectional views of FIGS. 2A and 2B are cross-sectional views taken along lines AA' and BB' in FIGS. 3A to 4C, and the corresponding layout diagrams of FIGS. Projection layout in line direction. 2A and 2B, on a silicon substrate 1, a transistor layer 100, a first wiring layer 101, a second wiring layer 102, a third wiring layer 103 , the fourth wiring layer 104 , the fifth wiring layer 105 and the sixth wiring layer 106 . The uppermost layer is a passivation film 117 .

[0045] FIG. 3A is a view showing a transistor layer 100. In a memory cell MC region of a silicon substrate 1, a transistor region is formed by selectively forming a component isolation insulating film 121 by the LOCOS method. Afterwards, in some regions of the t...

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Abstract

There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a storage node of the portion of the SRAM memory cell and achieving high capacitance formation of a storage capacitor. The Shadow RAM is provided with a relay wiring layer between a wiring layer corresponding to the storage node and a lower electrode of the ferroelectric capacitor, a wiring corresponding to the storage node is connected to a relay wiring via a first and a second opening portion arranged at a first interval and the lower electrode of the ferroelectric capacitor is connected to a relay wiring via a third and a fourth opening portion arranged at a second interval narrower than the first interval.

Description

technical field [0001] The present invention relates to static random access memory (SRAM), particularly a kind of image RAM, and it has the memory unit that adds ferroelectric capacitor to form in SRAM, when it is powered, is used for reading and reading SRAM unit at a high speed Write, when no power is supplied, maintains non-volatile memory in the ferroelectric capacitor. Background technique [0002] A conventional static random access memory (SRAM) includes a flip-flop composed of two CMOS inverters, as shown in the circuit diagram of FIG. 1A. Furthermore, the drains of the NMOS transistors Q0 and Q1 constituting flip-flops are made to constitute storage nodes N0 and N1. The two storage nodes N0 and N1 are respectively connected to the negative bit line BLN and the positive bit line BLT through NMOS transistors Q4 and Q5 serving as transfer gates. Gates of NMOS transistors Q4 and Q5 constituting transfer gates are connected to a common word line WL. The negative bit ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H10B10/00G11C14/00H10B20/00
CPCG11C14/00H10B10/00
Inventor 奈仓健三轮达
Owner NEC ELECTRONICS CORP
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