Method for making non-volatile memory with shallow junction

Abstract

A manufacturing method of the non-volatile memory having a shallow junction includes a grid structure on the substrate and the grid structure coprises an electron-catching layer and a conducting layer. A doped gap wall is formed on the side wall of the gap structure and then a plurality of embedding wires are formed in the substrate beside the grid structure. Further, the heat treatment is performed so that the dopant can diffuse into the substrate near the embedding wire through the doping gap wall.

Description

technical field [0001] The present invention relates to a method of manufacturing an integrated circuit device, and more particularly to a method of manufacturing a non-volatile memory with a shallow junction. Background technique [0002] Memory components can be widely used in many ways. Usually, a memory device includes thousands of memory cells, and these memory cells are arranged in rows and columns to form an array. In the memory cell array, the memory cells in the same row or column are connected by a common wire, and this common wire is called a word line; and the vertical wire related to data transmission is called a bit line. (bit line). The common structure of a memory device consists of an array of memory cells, each of which is located at the intersection of a parallel array of buried wires formed in a semiconductor substrate and a vertical array of wires formed on the substrate (intersection) on. Such a memory structure is, for example, a read-only memory (...

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Problems solved by technology

This diffusion often causes the source / drain extensions to extend vertically into the semiconductor substrate, making shallow source / drain extensions difficult to maintain

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