EEPROM memory chip with multiple use pinouts

A storage chip and chip technology, applied in information storage, static memory, read-only memory, etc., can solve unrealistic problems and achieve the effect of reducing the number of pins

Inactive Publication Date: 2003-08-06
SANDISK CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, pin count, arrangement and size are often standardized to a package of, say, 28 pi

Method used

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  • EEPROM memory chip with multiple use pinouts
  • EEPROM memory chip with multiple use pinouts
  • EEPROM memory chip with multiple use pinouts

Examples

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Embodiment Construction

[0012] figure 1 It is a typical embodiment that includes many aspects of the present invention. It is a partial block diagram of a non-volatile memory chip 100 used in the system described in the pending U.S. patent application entitled "Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks (Flash EEPROM system capable of simultaneously programming multiple data areas and storing physical block characteristics in other designated blocks)", and has been included in the above reference. The chip includes a high voltage generator 110 , a multiplexing circuit / input buffer MUX 130 , and a device selection circuit 120 including a chip address decoder 121 and a comparison module 123 . Other peripheral components and the actual bank of memory cells have been removed to simplify the discussion. Also, only those inputs corresponding to the pins discussed below are explicitly labeled, while other...

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Abstract

The present invention reduces the demand on the number of pins of an EEPROM memory chip or flash EEPROM chip by multiplexing a subset of the pins between the high voltage generator circuit of the chip and the chip select circuit. When the chip receives an enable signal, the subset of pins are connected to the chip's charge pump circuit allowing it to be connected to an external set of capacitors through these pins. When the enable signal is de-asserted, the subset of pins are connected to the chip select circuit. When the chip is part of an array of chips, this allows this subset of pins to be used to assign a chip address for determining the chips position in the array. When a number of chips are placed in an array, one (or more) of the chips supplies the other chips in the array with the high voltage and current needed for erasing and programming. To be able to do this, this chip is enabled and connected through the subset of pins to the external capacitors. The other chips are not enabled and use the subset of pins to determine their array address. As the enabled chip (or chips) can not have its address specified in this way, it is placed in a predetermined location within the array and this predetermined address is supplied to the chip select circuit in response to the enable signal.

Description

technical field [0001] The present invention mainly relates to a memory chip, and more specifically relates to an external connection of an electrically erasable and programmable read-only memory (EEPROM) and a Flash EEPROM chip. Background technique [0002] A non-volatile memory system, such as a Flash EEPROM, consists of many memory chips. Each chip includes a set of memory cells and associated peripheral circuits, which are connected externally by a set of pins. Instructions, addresses, and data information are passed through these pins. In addition, in EEPROM and Flash memory, there is usually a set of pins used to connect the charge storage outside the chip. [0003] The voltages required to program and erase EEPROM cells are generally higher than the normal operating voltages required to read memory. In order to generate a higher voltage Vpp, a high voltage generating circuit is used. This high voltage generating circuit is a DC (direct current) to DC voltage conv...

Claims

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Application Information

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IPC IPC(8): G11C16/06G11C5/06G11C16/30
CPCG11C16/30G11C5/066G11C16/02
Inventor 劳尔·阿德里安·塞尼亚汉德克尔·N·夸德森嘉·迈罗特雷
Owner SANDISK CORP
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