Erase scheme for non-volatile memory

A non-volatile storage and removal technology, applied in the field of erasing non-volatile storage units, can solve problems such as reading errors and data reliability issues
CN1449024AInactive Publication Date: 2003-10-15MACRONIX INT CO LTD
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
MACRONIX INT CO LTD
Publication Date
2003-10-15
Estimated Expiration
Not applicable Β· inactive patent

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Abstract

The present invention relates to the erasing method of non-volatile memory unit. The non-volatile memory unit has substrate, the first source / drain, the second source / drain, channel region between the first source / drain and the second source / drain, grid on the channel region, and non-conductive charge trap material between the first insulating layer and the second insulating layer and between the grid and the channel region. The erasing method of the non-volatile memory unit includes the following steps: executing hot hole erasing program of implanting hot holes to non-conductive charge trap material to remove the first electron stored therein while partial holes existing in the second insulating layer; and subsequent executing mending program to remove the holes existing in the second insulating layer.
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Description

technical field

[0001] The invention relates to a method for erasing data of a semiconductor storage device, in particular to a method for erasing data of a programmable read-only memory with charge trapping dielectric material on the gate. Background technique

[0002] At present, the non-volatile memory for storing data is quite common and widely used, and it is applied in a wide range of fields, such as various portable communication systems. US Patent No. 5,768,192 (Eitan) discloses a device, method of programming, and method of reading data from a programmable read-only memory (PROM) cell having a charge-trapping dielectric layer between two silicon oxide layers.

[0003] figure 1 It is a cross-sectional view of the structure of a read-only memory (PROM) cell disclosed in US Patent No. 5,768,192, wherein the conventional technology utilizes ONO as a gate insulating layer. This type of PROM can utilize the act of trapping electrons in the silicon nitride layer 20 adjac...

Claims

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