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Erase scheme for non-volatile memory

A non-volatile storage and removal technology, applied in the field of erasing non-volatile storage units, can solve problems such as reading errors and data reliability issues

Inactive Publication Date: 2003-10-15
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, the traditional band-to-band hot hole erasing method will lead to serious read disturbances, because when erasing data, if there are redundant holes remaining in the silicon oxide layer 18, the lateral electric field of the short channel will be strengthened. And help unintended electrons cross the oxide layer, causing data reliability problems

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  • Erase scheme for non-volatile memory

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Embodiment Construction

[0021] figure 2 It is a cross-sectional view of the structure of the read-only memory unit according to the embodiment of the present invention and the bias voltage applied when performing band-to-band hot hole erasing. The P-type substrate 32 has two N+ junctions separated by a channel region, one of which is a source 34 and the other is a drain 36 . Above the channel region is a silicon dioxide layer 38, which is an insulating layer, preferably with a thickness of 80-100 angstroms. Overlying the silicon dioxide layer 38 is a silicon nitride layer 40 approximately 100 Angstroms thick. The silicon nitride layer 40 is a storage storage layer capable of trapping thermal electrons injected into the silicon nitride layer 40 . Another silicon dioxide layer 42 is formed on the silicon nitride layer 40, preferably with a thickness of 80-100 angstroms. The silicon dioxide layer 42 isolates the conductive gate 44 formed on the silicon dioxide layer 42. In addition, a gate electrode ...

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Abstract

The present invention relates to the erasing method of non-volatile memory unit. The non-volatile memory unit has substrate, the first source / drain, the second source / drain, channel region between the first source / drain and the second source / drain, grid on the channel region, and non-conductive charge trap material between the first insulating layer and the second insulating layer and between the grid and the channel region. The erasing method of the non-volatile memory unit includes the following steps: executing hot hole erasing program of implanting hot holes to non-conductive charge trap material to remove the first electron stored therein while partial holes existing in the second insulating layer; and subsequent executing mending program to remove the holes existing in the second insulating layer.

Description

technical field [0001] The invention relates to a method for erasing data of a semiconductor storage device, in particular to a method for erasing data of a programmable read-only memory with charge trapping dielectric material on the gate. Background technique [0002] At present, the non-volatile memory for storing data is quite common and widely used, and it is applied in a wide range of fields, such as various portable communication systems. US Patent No. 5,768,192 (Eitan) discloses a device, method of programming, and method of reading data from a programmable read-only memory (PROM) cell having a charge-trapping dielectric layer between two silicon oxide layers. [0003] figure 1 It is a cross-sectional view of the structure of a read-only memory (PROM) cell disclosed in US Patent No. 5,768,192, wherein the conventional technology utilizes ONO as a gate insulating layer. This type of PROM can utilize the act of trapping electrons in the silicon nitride layer 20 adjac...

Claims

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Application Information

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IPC IPC(8): C07D493/22G11C16/02A61K31/357A61K31/365A61K36/00A61K36/28A61P33/06G11C11/34G11C16/04G11C16/34H01L21/8239H01L21/8247H01L27/10H01L27/115H01L29/788H01L29/792
CPCG11C16/0475G11C16/3404G11C16/3418A61K31/365A61P33/06
Inventor 叶致锴蔡文哲卢道政
Owner MACRONIX INT CO LTD
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