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Processor apparatus, information processor using the same, compiling apparatus and method thereof

A processor, command processing technology, applied in electrical digital data processing, preventing unauthorized use of memory, instruments, etc., can solve problems such as difficulty in maintaining the protection range correctly

Inactive Publication Date: 2004-01-21
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, if a memory access occurs beyond the module, it is difficult to properly maintain its protection

Method used

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  • Processor apparatus, information processor using the same, compiling apparatus and method thereof
  • Processor apparatus, information processor using the same, compiling apparatus and method thereof
  • Processor apparatus, information processor using the same, compiling apparatus and method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0099] This aspect relates to a processor device. figure 1 It is a block diagram of the processor device according to Embodiment 1 of the present invention.

[0100] Such as figure 1 As shown, the processor device 10 is connected to a memory device 30 and an I / O device 40 etc. via a bus 20 . Also, the processor device 10 is equipped with the following structural components.

[0101] The command processing unit 1 reads in and sequentially executes the program on the memory device 30 via the bus 20 , and performs input and output with the I / O device 40 .

[0102] Here, in this mode, an MMU (memory management unit) is set between the command processing unit 1 and the bus 20, the command processing unit 1 and the MMU2 use logical addresses for input and output, and the MMU2 performs logical address / physical address conversion, but For example, the MMU may be omitted, and the command processing unit 1 may input and output physical addresses.

[0103] Furthermore, in the process...

Embodiment approach 2

[0156] This method involves figure 1 The shown compiling device based on the address register 3 and the first range information register 4 supports pointers with range information. In addition, in the case of generating executable code from source code, methods such as compiling and linking are usually combined according to stages, but in this specification, a series of methods from source code to generation of executable code are collectively referred to as compile.

[0157] image 3 is a block diagram of a compiling device according to Embodiment 2 of the present invention. Of course, the compiling device 51 shown in FIG. 2 generates the execution code 60 from the source code 52 described in a programming language (for example, c / c++ language, Pascal, etc.) that can directly manipulate pointers.

[0158] In this source code 52, as described in Embodiment 1, pointers with range information are used, so no special description is required.

[0159] In FIG. 2 , the source an...

Embodiment approach 3

[0178] This method involves figure 1 The illustrated compiling device is supported by a pair of a program counter 5 and a second range information register 6 to perform range protection of address values.

[0179] Figure 5 is a block diagram of a compiling device according to Embodiment 3 of the present invention. Such as Figure 5 As shown, the compiling device 71 generates an execution code 81 based on the source code 72 described in the same programming language as in the second embodiment, and includes the main components described below.

[0180] The source analyzing unit 73 determines the forwarding destination of the code according to the discrimination condition. The function code range is stored in the function code range storage memory 79 . In the execution code memory 78, the generated execution code is stored.

[0181] The function code range analysis unit 74 analyzes the function code range in the execution code memory 78 when the source analysis unit 73 det...

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Abstract

A processor device comprises: an instruction processing unit, which reads and successively executes a program on a memory device; an address register, which stores the absolute address of a pointer in the program; a range information register, which stores range information concerning the pointer by using the absolute address; and an exception generating unit, which, when the instruction processing unit accesses the memory device using the pointer concerning the address register, inputs the output of the instruction processing unit and the range information in the range information register and, if there is a range violation of the memory device, outputs an exception signal S1 to the instruction processing unit. A pointer and its access range information are associated in an inseparable manner and accurate access protection is performed even beyond a module.

Description

technical field [0001] The invention relates to a processor device with memory protection function, a compiling device and related technologies. Background technique [0002] The existing memory protection technology in the computer system is almost completed by the processor or the compiler alone, and the combination-based memory protection technology is just an extension of this technology. [0003] As the memory protection technology in the processor, there is a segment protection technology using a register device indicating an address range such as a segment register, setting the accessible range of the memory, and installing a memory management unit (MMU) etc. in the processor paging protection technology, etc. [0004] In these techniques, exceptions are generated at the time of incorrect access by setting the access range only to the OS operating in the privileged mode of the processor. [0005] As a memory protection technique based solely on a compiler, there is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/14G06F9/45G06F11/36
CPCG06F11/3624G06F9/3861
Inventor 渕上竜司米泽友纪大槻博树田中义辉
Owner PANASONIC CORP
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