Method for forming grid electrode of semiconductor

Abstract

First, a stack architecture including a conductor layer and a topping layer is formed on substrate. Next, a high-density plasma dielectric layer is formed and the topping layer is exposed, and top part of the high-density plasma dielectric layer is higher than the top part of the conductor layer. Then, the topping layer is removed. A concavity part is formed on the conductor layer since the high-density plasma dielectric layer is higher than the top part of the conductor layer. Finally, oxidation gap wall is formed sidewall at concavity part. A conductor layer deposited on substrate and covering the concavity part is connected to original conductor layer so as to form a grid electrode of a semiconductor device.

Description

technical field [0001] The present invention relates to a method for forming a semiconductor device, and in particular to a method for forming a semiconductor gate. Background technique [0002] At present, in the semiconductor manufacturing process, there is a gate manufacturing method that does not require chemical mechanical polishing (CMP) as a planarization process, and has gradually attracted attention due to its advantages of environmental protection and low cost. This method of manufacturing a semiconductor gate mainly utilizes a cap layer formed on the gate, cooperates with a high density plasma (HDP) oxide layer deposited on the substrate, and then uses hydrogen fluoride to (HF) Remove part of the high-density plasma oxide layer until the top cover layer is exposed, and then use the step of removing the top cover layer to remove the redundant high-density plasma oxide layer on the gate to obtain a flat surface with high density Plasma oxide layer. Moreover, after...

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Problems solved by technology

[0003] However, the above-mentioned method of forming a semiconductor gate is prone to defects in the interface between the high-density plasma oxide layer and the gate, and there is a risk of penetrating through the substrate when forming a larger upper portion of the gate subsequently, resulting in a single Bit (single bit) failure, thereby affecting its reliability (reliability)

Moreover, when semiconductor devices are miniaturized, in order to achieve the purpose of increasing the upper surface of the gate and reducing the size of the device at the same time, the distance between the two gates must be shortened as much as possible, so it is easy to cause misalignment in the subsequent lithography manufacturing process. Device failure caused by (mis-alignment), thereby reducing the gate coupling ratio (GCR for short)

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