Semiconductor device and its driving method
A driving method and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of difficult multi-value storage characteristics, difficult to obtain polarization states correctly, difficult to control, etc., and achieve stable information retention. , The effect of suppressing manufacturing cost and high separability
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no. 1 Embodiment approach
[0117] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0118] figure 1 It is a plan view of the multivalued memory according to the embodiment of the present invention. in addition, figure 2 Yes figure 1 The profile of II·II line, image 3 Yes figure 1 Sectional view of line III-III. exist figure 1 , figure 2 , image 3 In , the same components are marked with the same symbols. and, figure 1 Only the topmost constructs are shown in solid lines. Additionally, with figure 2 , image 3 For the similar parts, some symbols are omitted for easy reading.
[0119] like figure 2 As shown, the multi-valued memory of the present embodiment has: a p-type silicon (Si) substrate 1; an element isolation film 5, which is made of silicon oxide formed on the silicon (Si) substrate 1 according to the LOCOS method. Composition; gate insulating film 7, it is to be formed by the silicon oxide on the active region o...
no. 2 Embodiment approach
[0172] Figure 19 , is a cross-sectional view showing the structure of the multi-valued memory according to the second embodiment of the present invention. As shown in the figure, the multi-valued memory of the present embodiment has: a p-type silicon (Si) substrate 1; a silicon oxide film; a gate insulating film, which is formed on a silicon (Si) substrate 1; a gate electrode / lower electrode 26, which is formed on the gate insulating film; Made of Pt / TiN; the first ferroelectric layer 27, which is made of BIT formed on the gate electrode / lower electrode 26, with a thickness of 100nm; the first upper electrode 29, which is formed on the first ferroelectric layer 27, and its width is less than half of the width of the gate electrode; the second ferroelectric layer 28 is formed on the first ferroelectric layer 27, and its width is half of the width of the gate electrode The thickness below is 400nm BIT; the second upper electrode 30 is formed on the second ferroelectric layer ...
no. 3 Embodiment approach
[0177] Figure 20 , is a circuit diagram showing a multi-valued memory according to a third embodiment of the present invention. As shown in the figure, the multi-valued memory according to the present embodiment is composed of a selection transistor Tr1 whose gate is connected to the word line WL and whose drain is connected to the bit line BL, and a source connected in parallel to the selection transistor Tr1. The ferroelectric capacitor MFM1 and the ferroelectric capacitor MFM2 are constituted. In the multivalued memory of this embodiment, the capacitor MFM1 and the capacitor MFM2 have different withstand voltages.
[0178] The multi-valued memory of this embodiment is called FeRAM, and reads information from the amount of current when the polarization of a capacitor is reversed. At this time, in the multi-valued memory of this embodiment, as described in the first and second embodiments, it is possible to obtain a plurality of stable and remnant polarization values by ...
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