Digital lock phase ring for producing multiple frequency point clock signal using one time delay chain

Abstract

Based on one input signal as reference, the digital phase locked loop generates one or more relatively stable clock signals after attenuating dithering in input signal. The phase locked loop includes following parts. Phase discrimination filter circuit compares difference between output clock and reference signal, and filters out high frequency component. Digital controlled oscillator (DCO) provides crystal oscillator for master clock. A time-delayed chain with taps is composed of cascaded same delay units in multiple stages. Compensation circuit eliminates influence caused by temperature and workshop deflection as well as selects suitable circuit from time-delayed chain to be output. One time-delayed chain can be provided for multiple circuits to use, and generates multiple frequency points at the same time. since new time sequence is utilized in the invention, only one time-delayed chain generates all frequency points so as to raise precision of clock as well as save area of chip.

Description

(1) Technical field [0001] The present invention relates to a digital phase-locked loop that uses a delay chain to generate clock signals of multiple frequency points, in particular to a digital phase-locked loop that is used to generate clock signals that provide timing for E1 and T1 data interfaces in a digital communication system ring. (2) Background technology [0002] In digital communication systems, it is often necessary to provide timing for E1 and T1 data interfaces. The clock signals of these timings are generated with reference to 1.544MHZ or 2.048MHZ input. The jitter is required to be very weak, have good stability, and meet ACCUNET RT1.5 And the specifications of ETS1, ETS300 01111. [0003] The above-mentioned clock signal can be generated by a digital phase-locked loop: the output signal is generated by the DCO, the difference between the reference signal and the output signal (or output frequency division) is compared by the phase detector, and the DCO is ...

AI Technical Summary

Problems solved by technology

[0006] Since two identical delay chains are required here, there are always differences between the two delay chains in the actual circuit. This mismatch will inevitably reduce the accuracy of the generated clock; Each 64-level delay chain and its selection circuit occupy a chip area of ​​about 2,000 gates. If multiple frequency points are to be generated, the area occupied by multiple chains and their selection circuits will double

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