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Semiconductor memory having self updating for reducing power consumption

A storage device, low-power technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problem of self-renewal operation power consumption increase

Inactive Publication Date: 2004-05-26
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0026] As the number of cells implemented in the memory device increases, the power consumption of the self-refresh operation in the memory device also increases

Method used

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  • Semiconductor memory having self updating for reducing power consumption
  • Semiconductor memory having self updating for reducing power consumption
  • Semiconductor memory having self updating for reducing power consumption

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0045] Hereinafter, the storage device of the present invention will be described in detail with reference to the accompanying drawings.

[0046] Figure 4 It is a block diagram of the self-updating operation of the storage device according to a preferred embodiment of the present invention.

[0047] As shown in the figure, the storage device related to refresh operation includes: a DRAM state controller 800, a self-refresh operation controller 700, a generator 600, a frequency divider 500, a self-refresh mode controller 100, a sensor The amplifier controller 900, a self-refresh termination controller 950, a unit area 400, a unit controller 200, and a power supply area 300. After receiving several control signals from the external circuit, such as / RAS, / CAS, / WE, / CS, CKE, CLK and similar signals, the DRAM state controller 800 can control the state of the storage device, that is, store, read Fetch and update status. After receiving a self-refresh entry signal (hereinafter ...

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Abstract

The present invention provides a memory device for reducing power consumption during a self-refresh operation performed for protecting data loss. For this object, in the present intention, the memory device for performing a refresh operation in a self-refresh period instigated for every constant time interval after entering into a self-refresh mode includes a low-power controller outputting a enable signal for enabling the power supply means during the self-refresh period after being enabled in the self-refresh mode; and a power supply means receiving the enable signal for supplying a low and a high voltages used in an internal circuit by using an external supply voltage and a ground voltage, wherein the low voltage is lower than the ground voltage and the high voltage is higher than the external supply voltage.

Description

technical field [0001] The present invention is about a dynamic random access memory device, and specifically, only about a memory device that reduces power for self-refresh operations. Background technique [0002] In general, semiconductor devices can be classified into dynamic random access memory (hereinafter referred to as DRAM) and static random access memory (hereinafter referred to as SRAM). An SRAM consisting of, for example, 4 transistors forming a latch protects stored data from loss as long as the power supply is not removed. However, DRAM, which consists of basic cells, where each basic cell is composed of a transistor and a capacitor, stores data in capacitors. According to the characteristics of the capacitor, the charge of the capacitor storing data is consumed in proportion to the storage time. Therefore, DRAMs using such capacitors require periodic refresh operations. [0003] The update operation includes the following cyclic steps. The first step is t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/407G11C11/406
CPCG11C2211/4067G11C11/406G11C11/40611G11C11/407
Inventor 金容欺
Owner SK HYNIX INC
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