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Non volatile memory

A storage circuit and semiconductor technology, used in information storage, static memory, electronic circuit testing, etc., can solve the problems of inability to increase the SA voltage of the sense amplifier, poor aging acceleration, etc.

Inactive Publication Date: 2004-06-02
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the case where the sense amplifier SA is formed with a thin film transistor, since the sense amplifier SA will be broken down when the voltage of the sense amplifier SA is increased, the voltage of the sense amplifier SA cannot be increased.
[0024] For example, the oxide film thickness of the thick film transistor is set to 6.5nm, and the oxide film thickness of the thin film transistor is set to 3.5nm, and the electric field stress applied to the oxide film during the aging test is 8MV / cm. MFT can apply 5.2V, but since only 2.8V potential difference can be applied between the pair of bit lines to which the sense amplifier SA is connected, aging acceleration is poor

Method used

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Experimental program
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Embodiment 1

[0035] figure 1 A structure of a semiconductor memory circuit having a normal operation mode and a burn-in test mode according to Embodiment 1 of the present invention is shown. This semiconductor memory circuit includes a memory cell array 1 including a plurality of memory cells MC arranged in a matrix. A pair of bit lines BL1 and / BL1 and a pair of bit lines BL2 and / BL2 are provided for the rows of the memory cell array 1 , while a plurality of word lines WL are provided for the columns of the memory cell array 1 . Memory cell MC is located at the intersection of a bit line and a word line WL, and is composed of one transistor and one capacitor.

[0036] exist figure 1 In the memory cell array 1, the bit line pair BL1 and / BL1 and the bit line pair BL2 and / BL2 are alternately arranged in the direction of the word line WL, and the bit line BL1, / BL1, BL2 and / BL2 are arranged in sequence. A half-pitch cell configuration in which multiple groups are repeated.

[0037] ex...

Embodiment 2

[0045] image 3 It shows the structure of a semiconductor memory circuit having a normal operation mode and a burn-in test mode according to Embodiment 2 of the present invention. exist image 3 In the memory cell array 1 of the semiconductor storage circuit, the pair of bit lines BL1 and / BL1 and the pair of bit lines BL2 and / BL2 are nested and combined in the direction of the word line WL, and the bit lines BL1, BL2, A quarter-pitch cell configuration in which groups of / BL1 and / BL2 are repeatedly arranged. Another structure of the semiconductor memory circuit, due to the figure 1 The semiconductor memory circuit is the same as that of the semiconductor memory circuit, so its description is omitted.

[0046] image 3 The aging test of semiconductor memory devices can also be used with figure 1 The semiconductor memory device is similarly performed. For example, when the potentials VBL1 and VBL3 are set to the H level and the potentials VBL2 and VBL4 are set to the L ...

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Abstract

The present invention relates to a semiconductor memory circuit which is capable of performing a burn-in test by applying a high potential difference between bit line pair even in the case a thin film transistor is used for a sense amplifier. A first short-circuiting transistor circuit for coupling first and second potentials to the first bit line pair and a second short-circuiting transistor circuit for coupling third and fourth potentials to the second bit line pair are formed by a thick film transistor and set in the semiconductor memory circuit.

Description

technical field [0001] The present invention relates to an aging test circuit for screening chips with latent defects associated with early defects by applying higher voltage than normal operation mode to memory cells in semiconductor memory circuits, especially DRAM chips. Background technique [0002] FIG. 4 shows the structure of a conventional semiconductor memory circuit. A conventional semiconductor memory circuit includes a memory cell array 1 including a plurality of memory cells MC arranged in a matrix. A pair of bit lines BL1 and / BL1 and a pair of bit lines BL2 and / BL2 are provided for the rows of the memory cell array 1 , while a plurality of word lines WL are provided for the columns of the memory cell array 1 . The memory cell MC is located at the intersection of the bit line and the word line WL, and each memory cell MC is a DRAM memory cell composed of one transistor and one capacitor. [0003] On both sides of the memory cell array 1, sense amplifier circ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/30G01R31/28G11C7/12G11C7/18G11C11/401G11C29/06G11C29/12
CPCG11C7/18G11C2207/005G11C29/12G11C7/12G11C2207/002G11C2029/1204G11C11/401
Inventor 月川靖彦
Owner RENESAS TECH CORP