Digital signal processor with a repeatable switching buffer memory

Abstract

A digital signal processor with switching over buffers mainly comprises a program control unit, an address generator unit, an instruction decoding unit, a digital data processing unit, an inner-chip digital data storage device, an outer-chip digital data storage device, a selector and a hit judgment logic equipment. The invention improves the existing buffer design, only by a the arrangement of a port, the buffer on the chip can be modified into conventional on chip internal memory, which enables accurate and efficient internal memory access operation when executing small programs.

Description

technical field [0001] The invention relates to a digital signal processor, in particular to a digital signal processor with a reswitchable buffer, belonging to the technical field of digital signal processing. Background technique [0002] The program of modern digital signal processing is getting bigger and bigger. If all the programs are read into the on-chip memory at one time, a lot of on-chip memory is needed, so that the very large chip area increases the cost a lot. But if off-chip memory is used, since off-chip memory requires more read and write cycles than on-chip memory, the efficiency of program operation will be very low. In order to solve the contradiction between efficiency and cost, a cache device is used in some modern digital signal processors (DSP). In 1987, "1987 IEEE International Solid State Circuits Conference (1987 IEEE International Solid State Circuits Conference)" published by the International Electrical Society IEEE published "A 60 ns CMOS DSP ...

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Problems solved by technology

However, if the nature of the on-chip memory cache is preserved, the program cannot know the exact content of the cache, so it cannot be accessed correctly

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