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Semiconductor device

A technology of semiconductor and conductor components, applied in the field of semiconductor devices, can solve problems such as difficulties

Inactive Publication Date: 2004-09-29
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, since the threshold value increases as the impurity concentration of the body increases, it is actually difficult to ensure a wide range of operating voltages by increasing the impurity concentration of the body.

Method used

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  • Semiconductor device
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no. 1 Embodiment approach —

[0038] In the first embodiment, an embodiment in which SiGe having a gradient composition is used as a material constituting a channel region and HDTMOS using a Si / SiGe heterojunction (hereinafter referred to as gradient composition SiGe-HDTMOS) will be described.

[0039] figure 1 (a), (b), and (c) respectively represent the schematic plan views of the structure of the p-channel tilted SiGe-HDTMOS of the present embodiment, figure 1 (a) The sectional view of the Ib-Ib line shown, figure 1 (a) Cross-sectional view along line Ic-Ic shown. Such as figure 1 As shown in (a) to (c), the tilted SiGe-HDTMOS of this embodiment includes a p-type Si substrate 10, a buried oxide film 11 with a thickness of about 100 nm formed in the Si substrate by implanting oxygen ions, etc., The semiconductor layer 30 is provided on the buried oxide film 11 . The semiconductor layer 30 is composed of an upper Si film 12 with a thickness of about 100 nm on the top of the SOI substrate, an Si buffer...

no. 2 Embodiment approach —

[0090] In the second embodiment, an embodiment in which SiC having a gradient composition and HDTMOS using a Si / SiC heterojunction (hereinafter referred to as gradient composition SiC-HDTMOS) is used as the material constituting the channel region will be described.

[0091] Figure 4 A cross-sectional view schematically showing the structure of the n-channel type tilted SiC-HDTMOS of the present embodiment. Such as Figure 4As shown, the inclined SiC-HDTMOS of this embodiment includes a p-type Si substrate 50, a buried oxide film 51 with a thickness of about 100 nm formed in the Si substrate by implanting oxygen ions, etc. The semiconductor layer 80. The semiconductor layer 80 is composed of an upper Si film 52 with a thickness of about 100 nm on the upper part of the SOI substrate, an Si buffer layer 53 with a thickness of about 10 nm epitaxially grown on the upper Si film 52 by UHV-CVD, and a Si buffer layer 53 on the Si buffer layer 53. Si with a thickness of about 15nm...

no. 3 Embodiment approach —

[0107] In the third embodiment, SiGe having a gradient composition is used as the material constituting the channel region, and HDTMOS (hereinafter referred to as gradient composition SiGe-HDTMOS) in which an undoped Si buffer layer is provided at the same time using a Si / SiGe heterojunction The implementation plan will be described.

[0108] Figure 6 A schematic cross-sectional view showing the structure of the p-channel type tilted SiGe-HDTMOS of the present embodiment. Such as Figure 6 As shown, the inclined SiGe-HDTMOS of this embodiment includes a p-type Si substrate 10, a buried oxide film 11 with a thickness of about 100 nm formed in the Si substrate by implanting oxygen ions, etc. The semiconductor layer 30. The semiconductor layer 30 consists of an upper Si film 12 with a thickness of about 100 nm on the top of the SOI substrate, an undoped Si buffer layer 33 with a thickness of about 30 nm epitaxially grown on the upper Si film 12 by UHV-CVD, Si with a thicknes...

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Abstract

A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1-xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1-xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.

Description

technical field [0001] The present invention relates to a semiconductor device functioning as a DTMOS or MISFET having a heterojunction active region, and more particularly to a semiconductor device operating at a low power supply voltage. Background technique [0002] In recent years, battery-driven portable information terminal devices have been widely used. In such devices, in order to prolong battery life, it is strongly required to reduce the power supply voltage without sacrificing high-speed operation. Lowering the threshold voltage is an effective way to realize high-speed operation even at a low power supply voltage, but in this case, there is a lower limit for the threshold voltage because the leakage current increases when the gate is turned off. [0003] Therefore, for example, as described in the document (F.Assaderaghi et.al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation," IEDM94 Ext.Abst.p.809), a solution such as Problem, a de...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/10H01L29/165H01L29/78H01L29/786H01L29/80
CPCH01L29/1054H01L29/165H01L29/78606H01L29/783H01L29/802H01L29/78687H01L29/78696
Inventor 井上彰高木刚原义博久保实
Owner PANASONIC CORP
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