Method for manufacturing flash memory

Abstract

The method includes steps: providing a substrate possessing memory cell zone and periphery circuit zone; forming tunnel dielectric layer on substrate in memory cell zone and forming underlayer on substrate in periphery circuit zone; forming patternized conducting layer of grid pole on substrate; forming dielectric layer between grids and protective layer on the substrate in sequence; then, removing out protective layer, dielectric layer between grids, first conducting layer and underlayer in periphery circuit zone, and forming dielectric layer of grid pole on base of periphery circuit zone, converting protective layer to oxide layer in memory cell zone. Finally, forming conducting layer on the substrate, patternizing conducting layer, oxide layer, dielectric layer between grids, conducting layer of grid pole, and patternizing second conducting layer in periphery circuit zone in order to form grid pole.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor device, and in particular to a manufacturing method of a flash memory (Flash Memory) device. Background technique [0002] Flash Memory (Flash Memory) components have the advantages of being able to store, read, and erase data multiple times, and the stored data will not disappear after power failure, so it has become a popular choice for personal computers and electronic devices. A widely used non-volatile memory element. [0003] A typical flash memory device uses doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). Moreover, the control gate is directly disposed on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunneling oxide layer (also known as Tunneling Oxide). So-called stacked gate flash memory). The flash memory element u...

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Problems solved by technology

[0009] In the above process, since the intergate dielectric layer 112 is very thin and fragile, it is easy to be damaged in the manufacturing process, such as the ashing process and cleaning process of the patterned photoresist layer 114

And the characteristics of the inter-gate dielectric layer 112 are deteriorated, and then the data retention characteristics of the flash memory are deteriorated.

[0010] On the other hand, in order to avoid damage to the top oxide layer in the inter-gate dielectric layer 112, a strong cleaning agent cannot be used in the photoresist stripping process, thus resulting in the inability to completely remove the photoresist and produce polymer residues. , resulting in metal contamination and poor gate quality

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