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Semiconductor memory device

A storage device and semiconductor technology, which is applied in semiconductor devices, information storage, semiconductor/solid-state device manufacturing, etc., can solve the problems of increasing chip area, increasing substrate mounting area, and increasing costs, achieving area reduction, cost reduction, The effect of reducing the installation area

Inactive Publication Date: 2005-01-26
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, in the above-mentioned background art, it is necessary to prepare another power supply voltage of the system, and while the wiring design of the LSI chip becomes complicated, two areas for power supply wiring must be provided, resulting in a decrease in the area of ​​the chip. increased
In addition, in the design of the system side using such a semiconductor device, two power supply circuits must be provided, which has the disadvantages of increasing the substrate mounting area and increasing the cost.
[0013] When the power supply on the system side is used as one system and another power supply circuit is installed on the chip, the area of ​​the chip is further increased.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0054] figure 1 It is a circuit diagram showing the structure of the semiconductor memory device according to the first embodiment of the present invention. exist figure 1 In , one word line, a word line driver circuit for driving it, and memory cells connected to the word line are shown.

[0055] exist figure 1 In , symbols 11 and 12 respectively denote a P-type channel driving transistor and an N-type channel driving transistor for driving the word line WL. Reference numeral 13 denotes an OR circuit constituted by a pull-up transistor 13a, a transmission gate 13b, and an inverter 13c. Reference numeral 14 denotes a time adjustment circuit. Reference numeral 15 denotes a capacitive drive circuit. Reference numeral 16 denotes a coupling capacitor whose one end is connected to the word line WL and the other end is connected to the output end of the capacitor driving circuit 5 . These constitute the word line driver circuit 410 . Reference numeral 17 denotes a storage ...

no. 2 Embodiment

[0074] Next, as the second embodiment of the invention, we will refer to the formation example of the coupling capacitance. image 3 side to explain.

[0075] The area demarcated by the dotted line 18 represents an area corresponding to the wiring layout of a memory cell of 1 bit. The word line wiring 21 arranges the portion divided by the dotted line 18 in a wiring design corresponding to a 1-bit memory cell. Adjacent wiring 22 formed on the same wiring layer as word line wiring 21 is connected to upper layer wiring 24 via hole 23, and all the separated adjacent wirings 22 are connected to upper layer wiring 24 as shown in the figure.

[0076] Adjacent wiring 22 , via hole 23 , and upper layer wiring 24 collectively arrange a portion demarcated by dotted line 18 similar to word line 21 in a wiring design corresponding to a 1-bit memory cell. The illustrated wiring can be configured by sequentially inverting the layout of the memory cell wiring in the lateral direction.

[...

no. 3 Embodiment

[0089] Next, with regard to the word line driving circuit in the third embodiment of the present invention, while referring to Figure 5 side to explain.

[0090] exist Figure 5 Among them, the word line drive circuit 30 outputs any one of all the word lines GWL1 - GWL128 running horizontally and any one of the column write control signals CWE1 - CWE8 running vertically. The column write control signals CWE1 to CWE8 are generated from the AND circuit 31 of the column decode signals CDEC1 to CDEC8 and the write control signal WE, respectively.

[0091] The word line driving circuit 30 is specifically as follows Image 6 structure shown. exist Image 6 , in the first embodiment having the representation with figure 1 Parts with the same functions are denoted by the same symbols, and their detailed descriptions are omitted.

[0092] for figure 1 The power supply of the capacitor driving circuit 15 is VDDL potential, at Image 6 In the capacitive drive circuit 15A, in t...

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Abstract

A semiconductor memory device comprises a word line drive circuit including a drive transistor, which drives a word line; a circuit for turning the drive transistor OFF right after an output of the word line drive circuit reaches a high level; and a word-line-voltage increasing circuit for increasing a voltage of the word line after the drive transistor turns OFF. The word-line-voltage increasing circuit includes a coupling capacitor one end of which is connected to the word line, and a capacitor drive circuit an output end of which is connected to the other end of the coupling capacitor. The capacitor drive circuit switches its output from a low level to a high level at turn-OFF timing of the drive transistor. The coupling capacitor includes a wiring line running along the word line.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to the construction of a word line driver circuit portion. Background technique [0002] Scaling of power supply voltage is very effective in reducing power consumption of CMOS semiconductor integrated circuits. However, in the method of scaling the power supply voltage, in the case of SRAM widely used in system LSIs, characteristic deterioration is likely to occur in the structure of the memory cell circuit. The main reason is that the fluctuation of the threshold voltage due to the effect of the back bias leads to a significant drop in the current capability when the power supply voltage is low. The back bias effect is caused by the potential of the source and the drain of the access transistor fluctuating according to the substrate potential. [0003] Therefore, the ability of the SRAM to increase the charge of the bit line during readout will decrease, increasin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/418G11C11/41G11C11/413H01L21/8244H01L27/11
CPCG11C11/413G11C11/419G11C11/418
Inventor 里见胜治赤松宽范
Owner PANASONIC CORP
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