Semiconductor memory device and method for making same

Abstract

A nonvolatile semiconductor memory device that uses inversion layers formed on a surface of its semiconductor substrate as data lines, which is capable of satisfying the requirements of suppressing both characteristic variation among memory cells and bit cost. In order to achieve the above object, in the memory device, a plurality of assist gates are formed so as to be embedded in a p-type well via a silicon oxide film, respectively and silicon nanocrystal grains of about 6 nm in average diameter used for storing information are formed without being in contact with one another. Then, a plurality of word lines are formed practically in a direction vertically to the assist gates and the space between adjacent those of the plurality of word lines is set under 1 / 2 of the width (gate length) of the word lines. Consequently, the inversion layers formed at side faces of the assist gates will be used as local data lines, thereby the resistance is lowered and the writing characteristic variation among memory cells in a memory mat is suppressed.

Description

technical field [0001] The present invention relates to a semiconductor memory device and a method of manufacturing the same, and particularly relates to a technique effective when applied to a nonvolatile semiconductor memory device using an inversion layer formed on a semiconductor substrate as a data line. Background technique [0002] As an application for data storage with excellent portability, flash memory which is a semiconductor nonvolatile memory has begun to be widely used. The price per bit of the above-mentioned flash memory has been decreasing rapidly year by year, and the rate of decrease is faster than expected only from miniaturization. [0003] Among the memory cell array systems of large-capacity flash memory for file use, there are NAND type in which memory cells are connected in series and AND type in which memory cells are connected in parallel as typical systems. The former NAND type is described, for example, in F.Arai et al, IEEEInternational Electr...

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Problems solved by technology

However, if a structure in which the local data line is connected to the global data line via a switch at a short distance is simply adopted, the number of memory cells per local data line decreases, and there is a problem that the area loss of the selection transistor portion increases.

In addition, especially with the advancement of miniaturization, the width of electrodes running parallel to the data lines is also required to be reduced. As a result, the wiring width of the inversion layer is also reduced, so the problem of resistance becomes significant.

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