Method of enhancing clear field phase shift masks by adding parallel line to phase 0 region

Abstract

A technique in which a boundary region is added to the outside parallel edge of phase zero (0) pattern defining polygons. This technique can reduce the need for optical proximity correction (OPC) and improve the manufacturability and patterning process window for integrated circuits. The technique can also set the width of both 0 and phase 180 polygons to specific sizes, making OPC easier to assign.

Description

technical field [0001] The present invention relates to integrated circuits and methods of fabrication thereof, and more particularly to generating phase shift patterns to improve patterning of gates, regions, structures, and layers requiring sub-nominal dimensions. Background technique [0002] A semiconductor device or an integrated circuit may contain a plurality of devices, such as transistors. Ultra-large ULSI may include complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs). Although known systems and fabrication allow the fabrication of many IC devices on a single IC, there is still a need to reduce the size of the IC device body, thereby allowing an increase in the number of devices on a single IC. [0003] One limitation to achieving reduced IC device size is known lithography capabilities. Photolithography is the manufacturing process by which patterns or images are transferred from one medium to another. The known IC photolithography ut...

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Problems solved by technology

As such, the patterning of the binary mask can be complicated and the fabrication window technology is limited

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