Synchronus scanning enable-condition prechargig CMOS trigger

Abstract

Based on existing trigger with conditional preshoot structure driven by clock signal in low voltage swing, the invention makes following modifications: reducing a additional high voltage power supplyin structure of simplified flip-latch in first stage; using two pieces of independent phase latch with same circuit parameters in single clock to form latch in second stage in order to ensure symmetrical output waveform; adding a scan and control circuit of having functions of enable control and scanning test. The invention also disclosed two CMOS triggers with modified structure: single end output, and synchronous reset. Under same testing condition, the invention saves more than 30% power consumption, smaller circuit area and improved delay performance of circuit.

Description

technical field [0001] The technical field of direct application of the "synchronous scanning enable condition precharge CMOS flip-flop" is low-power flip-flop circuit design. The proposed circuit is a kind of CMOS flip-flop circuit unit with scanning and enabling logic functions suitable for low power consumption circuits. Background technique [0002] With the advancement of CMOS integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the energy consumed by the clock network accounts for a high proportion of the total energy consumption of the entire circuit; among them, in the working state of the circuit, the energy consumed in the clock interconnection network and timing The ener...

AI Technical Summary

Problems solved by technology

However, the problem with the SAFF_CP circuit is that because the output latch circuit adopts a cross-coupled NAND2 (NAND2: two-input NAND gate) structure, the delay of the rising edge and the falling edge of the output of the flip-flop circuit are extremely asymmetrical. , presenting a potential problem for circuit units using

The advantage of this structure is that the logic function is intuitive and clear, and the implementation is simple, but relatively speaking, the number of transistors is relatively large (each tri-state gate is composed of four transistors), and at the same time, in order to ensure the driving ability and delay performance, the size of the transistors is usually relatively large. Big

This brings an increase in area and power consumption

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