Novel anti-noise high-speed domino circuit

Abstract

This invention belongs to large scale digital integration circuit technique field and relates to one new anti-noise domino digital logic circuit, which Uses one thin impulse generator effective control dynamic points to make the output dynamic point keep original level in the noise situation to realize strong anti-noise property and Adopts pull network parallel structure to eliminate current compactor to work under high frequency.

Description

technical field [0001] The invention belongs to the technical field of large-scale digital integrated circuits, and in particular relates to an anti-noise high-speed domino circuit applicable to dynamic logic circuits. Background technique [0002] Dynamic CMOS logic is a widely used logic form. It is proposed on the basis of complementary CMOS logic in order to improve the operating speed of the circuit and reduce the number of PMOS transistors connected in series in complex gate circuits. Such as figure 1 Shown is a 4-input OR gate implemented in complementary CMOS, figure 2 Is its corresponding "footless transistor" (footless) dynamic CMOS gate circuit. The operation of the complementary CMOS gates is completely static, while the operation of the dynamic CMOS gates works under the clock pace coordination. When CLOCK is low level, the circuit is in the pre-charging stage, and the dynamic point F is charged to high level, at this time the input is invalid, and must be s...

AI Technical Summary

Problems solved by technology

However, since KEEPER still exists in the stage of dynamic point level transition, increasing its size will definitely affect the speed, and reducing the size will affect the anti-noise ability, and the trade-off between speed and anti-noise still exists

So far, there is no circuit structure and technology designed for multi-input dynamic gate circuits that completely abandon the KEEPER structure.

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