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Peration method for nonvolatile memory

An operation method and a non-volatile technology, applied in the operation field of non-volatile memory, can solve the problems of lack of flexibility, inability to erase memory elements, inconvenient memory operation, etc., and achieve the effect of improving performance and high operational flexibility

Inactive Publication Date: 2007-02-21
POWERCHIP SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, for this kind of high-density non-contact memory, the memory of the same column must be programmed or erased at the same time, that is to say, the memory uses a fixed-size block as the erasing unit of the storage unit.
In this way, the memory element cannot be erased for a single storage unit, so there are considerable restrictions on the way of writing and erasing data in the memory, which makes the operation of the memory very inconvenient and lacks flexibility

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  • Peration method for nonvolatile memory
  • Peration method for nonvolatile memory
  • Peration method for nonvolatile memory

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Embodiment Construction

[0037] figure 1 Shown is a schematic circuit diagram of a non-volatile memory cell array according to a preferred embodiment of the present invention. In this embodiment, three columns of memory cell columns are taken as an example for illustration. figure 2 What is shown is a structural cross-sectional view of a non-volatile memory according to a preferred embodiment of the present invention. image 3 What is shown is a schematic diagram of the operation of a non-volatile memory according to a preferred embodiment of the present invention. figure 2 and image 3 Only one row of memory cells is shown in , and 6 memory cells in one row of memory cells are taken as an example for illustration.

[0038] Please refer to figure 1 , the non-volatile memory cell array, including at least the word line WL 1 ~WL 3 , bit line BL 1 ~BL 7 , main line SL 1 ~SL 6 and storage unit Q 11 ~Q 63 . storage unit Q 11 ~Q 61 , storage unit Q 12 ~Q 62 , storage unit Q 13 ~Q 63 Mem...

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Abstract

The method for operating non-volatile memory storage is suitable to operation of a row of memory cells. The row of memory cell includes at least main body layer in silicon substrate on an insulating layer, multiple floating grids on the main body layer, multiple source poles / drain poles in the main body layer between two adjacent floating grids, and control pole positioned on the floating grid. When carrying out erasing operation, the method applies first voltage to area of first source pole / drain pole selected from row of memory cells, applies second voltage to area of second source pole / drain pole in order to erase zone of memory cell area between first source pole / drain pole and second source pole / drain pole.

Description

technical field [0001] The invention relates to an operating method of a memory element, in particular to an operating method of a non-volatile memory element. Background technique [0002] Among all kinds of non-volatile memory products, it has the advantages of multiple data storage, reading, erasing, etc., and the stored data will not disappear after power off. Program read-only memory (EEPROM) has become a memory element widely used in personal computers and electronic equipment. [0003] On the other hand, with the development of integrated circuit manufacturing technology, the demand for component integration (Integrity) is getting higher and higher, and the size of components is shrinking day by day. In order to cope with this trend, US Patent No. 5796142 proposes a high-density contactless memory. Since the adjacent memory cells of the memory share the same source / drain region, and the memory cells are closely connected, the element size is small, the integration d...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H10B69/00
Inventor 张格荥黄丘宗
Owner POWERCHIP SEMICON CORP