Chip packaging body without kernel dielectric layer and stack chip packaging structure

Abstract

This invention relates to a chip package body without core dielectric layers and its stacked chip package structure, in which, the body includes a pattern circuit layer, a chip, a welded-cover layer, a package colloid and many external connecting terminals, in which, the pattern circuit layer has a relative first surface and a second surface, the chip is set on the first surface and electrically connected to the circuit layer, the welded-cover layer is matched on the second surface and has multiple first open-ends to expose part regions of the pattern circuit layer, the package colloid with multiple through holes covers the pattern circuit layer and fixes the chip on it, the external connecting terminals are matched in the through holes and the conduction posts are connected to the circuit layer electrically.

Description

technical field [0001] The invention relates to a stacked chip packaging structure of a chip package, in particular to a thin chip package without a core dielectric layer and a stacked chip package structure thereof. Background technique [0002] In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. In terms of product appearance, the design of electronic products is also moving towards the trend of light, thin, short and small. In order to achieve the above purpose, many companies incorporate the concept of systemization when designing circuits, so that a single chip can have multiple functions, so as to save the number of chips configured in electronic products. In addition, as far as electronic packaging technology is concerned, in order to meet the design trend of light, thin, short, and small, the packaging design concept of multi-chip module (MCM) and chip scale package (chip scale package) have also bee...

AI Technical Summary

Problems solved by technology

Therefore, if the thickness of the core dielectric layer cannot be effectively reduced, it will inevitably cause great obstacles in reducing the thickness of the chip packages 200a and 200b.

[0006] Of course, once the chip packages 200a and 200b encounter a bottleneck in reducing the thickness, the overall thickness of the stacked chip package structure 50 will not be significantly reduced, and thus the packaging density of the stacked chip package structure 50 will not be effective. improvement

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