Negative resistance device

Abstract

A negative resistance device (NRD) has a MOSFET-like structure, and is biased by: shorting the gate and source together at a fixed applied potential and applying a different fixed potential to the drain, and sweeping the bulk potential towards the drain potential, causing the bulk current to exhibit a negative resistance characteristic. The NRD may be used in a memory circuit (10) in which a resistor (R) is connected between the bulk (2) and a fixed potential. Two States of the circuit at which the current through the resistor matches that through the bulk of the NRD are stable, providing for bistable memory operation.

Description

[0001] The invention relates to electronic circuit memories.PRIOR ART DISCUSSION[0002] At present, the two primary volatile memory technologies in use are Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).[0003] Dynamic Random Access Memory (DRAM) is a volatile random-access memory that stores information as a charge on a capacitor. This capacitor leaks charge with time and hence the memory needs to be periodically refreshed by the peripheral circuitry to retain its memory content. DRAM memories cannot match the speed of the central processor unit (CPU) due to charging current limits (during memory read / write operations) and destructive reading which necessitates rewrite operation. However, DRAM is the least expensive semiconductor memory available on the market today and hence is used in most computers as the core memory. DRAM cells consist of one transistor and one capacitor.[0004] Static Random Access Memory (SRAM) is as fast as the CPU and is capable of ...

AI Technical Summary

Problems solved by technology

This capacitor leaks charge with time and hence the memory needs to be periodically refreshed by the peripheral circuitry to retain its memory content.

DRAM memories cannot match the speed of the central processor unit (CPU) due to charging current limits (during memory read / write operations) and destructive reading which necessitates rewrite operation.

However, DRAM is the least expensive semiconductor memory available on the market today and hence is used in most computers as the core memory.

However, this added functionality is area-intensive because SRAM memory cells consist of either four or six CMOS transistors.

However, because the device uses the on-state of the FET where the threshold voltage of the device is exceeded to generate negative resistance, there is a standby power consumption in the order of .mu.W for the device.

Another problem is that oxide is degraded over time because of injection of a significant number of hot carriers into the oxide.

However, standby power is excessive and in the order of .mu.W to mW and this prevents this device from large scale integration.

However, the standby power consumption in this device is still of the order of .mu.W.

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