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Semiconductor and method of fabricating

a technology of semiconductors and manufacturing methods, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of negative charge on the wafer surface, discharge damage, and/or gate oxide blowout, so as to reduce the potential drop across the semiconductor wafer and minimize the effect of harmful effects

Inactive Publication Date: 2001-08-23
IBM CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0006] The object of the present invention is to at least minimize and if not, entirely eliminate, the potential drop across the semiconductor wafer and especially across a gate oxide during plasma and ion beam processing. Another object of the present invention is to minimize any harmful effects caused by potential drop across the wafer during processing.
[0007] The present invention provides a sacrificial structure and fabrication method which ensures that the potential drop across any gate oxide is at least reduced, if not entirely eliminated, during plasma and ion beam processing. The present invention provides a removable or sacrificial conductive strap or spacer, which provides a conductive path around insulating layer such as the gate oxide to thereby eliminate any damage to the insulating layer.

Problems solved by technology

However, processes such as plasma deposition, plasma etching and ion implantation contribute to charging damage, leakage paths and / or gate oxide blow out.
This potential drop can result in wafer charging, leakage paths, and breakdown of dielectric layers (see FIG. 1).
This same problem occurs when employing ion beam techniques since such result in a positive charge on the wafer surface due to ion bombardment from the ion beam.
The problem due to the potential drop across the wafer is particularly pronounced when dealing with relatively thin dielectric layers such as about 40 to about 50 angstroms which are especially sensitive to being damaged.

Method used

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  • Semiconductor and method of fabricating
  • Semiconductor and method of fabricating
  • Semiconductor and method of fabricating

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Embodiment Construction

[0014] The present invention provides a sacrificial structure and fabrication method for ensuring that the potential drop across an insulating layer such as a gate oxide is reduced during damaging plasma and / or ion beam processing. For instance, FIG. 1 illustrates typical prior art structure comprising a semiconductor substrate 6 with a gate oxide 8 thereon and a gate conductor 10 located above gate oxide 8. When subjected to ion beam or plasma processing, a potential drop will exist between the gate conductor 10 and the exposed surface of semiconductor substrate 6. As discussed above, this potential drop can result in wafer charging, leakage paths, and especially dielectric breakdown of the gate oxide, particularly in structures wherein such is relatively thin.

[0015] Reference to FIGS. 2-10 illustrates various means for overcoming this problem. For instance, FIG. 2 illustrates a semiconductor substrate 6 such as a silicon substrate. A thin gate insulator 8 is grown on or deposited ...

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Abstract

Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and / or plasma processing; and a method for fabricating.

Description

[0001] The present invention is concerned with a semiconductor structure and method of fabricating. More particularly, the present invention is concerned with eliminating potential drop across a semiconductor wafer that typically occurs during processing. According to the present invention, a sacrificial or removable conductive strap is coupled to the semiconductor substrate and conductor where desired, for maintaining a common voltage between the conductor and substrate.BACKGROUND OF INVENTION[0002] In the manufacture of semiconductive devices, the steps of depositing layers and etching selected portions of layers which constitute the final chip in many cases employ ion beam and / or plasma processes. However, processes such as plasma deposition, plasma etching and ion implantation contribute to charging damage, leakage paths and / or gate oxide blow out. In particular, during plasma processes, the semiconductor wafer surface becomes negatively charged causing a potential drop across t...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/28
CPCH01L21/28017H01L21/28176H01L21/28194H01L21/28211H01L21/28247
Inventor BROOKS, DANIEL S.CHAPMAN, PHILLIP F.CRONIN, JOHN E.WISTROM, RICHARD E.
Owner IBM CORP