Split common source on eeprom array

Abstract

An EEPROM having reduced circuit loading of a high voltage write pulse by dividing an array of bit cells into two or more switchable common source segments. Only common source segments containing the bit cells being written to are connected, the other common source segments remain unconnected and do not contribute substantially to loading of the write pulse. Having multiple switchable common segmentations reduces the amount of parasitic capacitance connected in the EEPROM array during a write operation, thus reducing loading on the write circuits. Also reducing the number of bit cells having the common source segments connected during a write operation reduces the amount of leakage current contribution which adversely affects the write operation.

Description

[0001] The present invention relates generally to Electrically Erasable Programmable Read Only Memory (EEPROM), and more particularly to an EEPROM array having a split common source for reducing Vpp loading during programming memory bit cells of the EEPROM array.BACKGROUND OF THE INVENTION TECHNOLOGY[0002] EEPROM is a class of nonvolatile semiconductor memory in which information may be electronically programmed into and erased from each memory element or bit cell. Each bit cell of the EEPROM comprises two metal oxide semiconductor field effect transistors (MOSFET), one of the MOSFETs has two gates and is used to store the bit information, and the other MOSFET is used in the selection of the bit cell. Illustrated in FIG. 1a is a cross-section elevation view of a semiconductor integrated circuit bit cell 200 comprising a storage MOSFET 202 having two gates, a memory cell gate 102 and a floating gate 104, one above the other. A source well 108 and common drain / source well 118 make up ...

AI Technical Summary

Benefits of technology

This segmentation results in faster write times, improved reliability, and scalable bit cell arrays with reduced power consumption, enabling higher capacity EEPROMs without increasing the drive capacity of the write circuits.

Problems solved by technology

The on-chip charge pump has limited charging capabilities to generate the Vpp+ pulse during a write operation.

A significant amount of capacitance and cell leakage currents load the output of the charge pump.

As EEPROM array bit densities increase, the on-chip charge pump of such a chip begins having trouble pulling the Vpp+ line to a reliable programming voltage during a write cycle.

Reducing the bit cell device leakage currents would also require larger device structures with a resultant increase in die size.

As higher bit capacity EEPROMs are being fabricated using smaller transistor structures, these attempts at improving cell writing reliability is counter productive or impossible to achieve.

Images