Information processing apparatus

Abstract

A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] The present application claims priority from Japanese Patent Application Serial No. 2004-021207, filed on Jan. 29, 2004, the content of which is hereby incorporated by reference into this application. FIELD OF THE INVENTION [0002] The present invention relates to an information processing apparatus comprising a CPU, a memory and a prefetch means. It particularly relates to an interruption routine thereof and a technique prefetching a target instruction of RTE (return from exception). Further it relates to a technique effectively applicable to prefetching a target instruction for branch to a subroutine and to storing a target instruction of RTS (return from subroutine). BACKGROUND OF THE INVENTION [0003] Recently, while the operating frequency of CPUs has remarkably increased than before, the increase of operating frequency of memories has gently increased compared with that of CPUs to meet the requirement for greater capacities. The resu...

AI Technical Summary

Benefits of technology

[0010] A first object of the present invention is to provide an information processing technique permitting effective prefetching, ensuring high performance and meeting a high-level requirement for real time performance even with an application involving many interruptions.

[0027] Since the RTS instruction buffer for storing the series of instructions regarding the target addresses of RTS instructions is updated with a series of instructions from the current instruction buffer, it is possible to reduce performance deteriorations due to contention in memory accessing for the updating of the cache or buffers.

Problems solved by technology

For this reason, in an application involving many interruptions, there still remains the problem of no improvement in performance.

Or in an application needing a high level of real time performance, there arises a problem that no sufficient time for interruptions can be secured.

Furthermore, according to the technique disclosed in Patent Reference 1 cited above, the accuracy of prefetcing the target instructions for branch is dependent on the capacity of a branch history table, and therefore involves a problem of a higher system price because enhancing its performance would require a high-speed and large-capacity RAM for the branch history table.

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