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Switch memory management using a linked list structure

a linked list and switch memory technology, applied in data switching networks, instruments, data processing applications, etc., can solve the problems of design constraints and design requirements becoming more and more complex, and achieve the effect of reducing clock speed and power consumption in network chips

Inactive Publication Date: 2005-10-20
AVAGO TECH WIRELESS IP SINGAPORE PTE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The invention is a memory management system that reduces clock speed and power consumption in a network chip. The system assigns pointers to free memory locations and links them together to create a linked list. A free head pointer is assigned to the beginning of the list, a free tail pointer is assigned to the end of the list, and an initial data pointer is assigned to the beginning of the list. The system also assigns a next memory location to the free head pointer, which indicates the beginning of a new list of free memory locations. The technical effect of this invention is to improve the efficiency of memory management in network chips."

Problems solved by technology

As speed has increased, design constraints and design requirements have become more and more complex with respect to following appropriate design and protocol rules and providing a low cost, commercially viable solution.

Method used

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  • Switch memory management using a linked list structure
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  • Switch memory management using a linked list structure

Examples

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Embodiment Construction

[0026]FIG. 1 is an example of a block diagram of a switch 100 of the present invention. In this example, switch 100 has 12 ports, 102(1)-102(12), which can be fully integrated IEEE compliant ports. Each of these 12 ports 102(1)-102(12) can be 10BASE-T / 100BASE-TX / FX ports each having a physical element (PHY), which can be compliant with IEEE standards. Each of the ports 102(1)-102(12), in one example of the invention, has a port speed that can be forced to a particular configuration or set so that auto-negotiation will determine the optimal speed for each port independently. Each PHY of each of the ports can be connected to a twisted-pair interface using TXOP / N and RXIP / N as transmit and receive protocols, or a fiber interface using FXOP / N and FXIP / N as transmit and receive protocols.

[0027] Each of the ports 102(1)-102(12) has a Media Access Controller (MAC) connected to each corresponding PHY. In one example of the invention, each MAC is a fully compliant IEEE 802.3 MAC. Each MAC c...

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Abstract

A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Description

REFERENCE TO RELATED APPLICATIONS [0001] This is a Continuation of application Ser. No. 09 / 855,670, filed May 16, 2001, which claims priority to U.S. Provisional Patent Application Ser. No. 60 / 237,764 filed on Oct. 3, 2000 and U.S. Provisional Patent Application Ser. No. 60 / 242,701 filed on Oct. 25, 2000. The disclosure of the prior applications identified above are hereby incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to a method and apparatus for high performance switching in local area communications networks such as token ring, ATM, ethernet, fast ethernet, and gigabit ethernet environments, generally known as LANs. In particular, the invention relates to a new switching architecture geared to power efficient and cost sensitive markets, and which can be implemented on a semiconductor substrate such as a silicon chip. [0004] 2. Description of the Related Art [0005] As computer performance has increased in recent...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F7/00G06F12/00H04L12/56
CPCH04L49/103Y10S707/99957Y10S707/99953
Inventor SOKOL, MICHAEL A.
Owner AVAGO TECH WIRELESS IP SINGAPORE PTE