Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device
a technology of integrated circuit device and semiconductor, applied in the field adjustment method of semiconductor integrated circuit device, can solve the problems of automatic increase of testing time, large application burden, and complex and expensive tester device, and achieve the effect of simplifying the design process
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first embodiment
[0054]FIG. 3 shows a circuit block diagram of the first embodiment for adjustment of the internal power source voltage VII. An adjustment signal EAD0> to be inputted from an external terminal T11 is inputted to one input terminal of a multiplexer 51. A predetermined signal FS0>, which is to be stored in a fuse circuit (or memory circuit) 41, is inputted to the other input terminal of the multiplexer 51. The multiplexer 51 is controlled by a test signal TS inputted to the external terminal T15. In adjustment test for the internal power source voltage VII, the adjustment signal EAD0> is selected. In a normal state after the adjustment signal is stored in the fuse circuit (or memory circuit) 41 after the adjustment test is completed, the predetermined signal FS0> is selected. The selected signal EAD0> or FS0> is decoded by a decoding circuit 61. A decoding signal D0> outputted from the decoding circuit 61 is inputted to the internal power source circuit 31.
[0055] The internal power sou...
second embodiment
[0080]FIG. 9 shows a major component circuit diagram according to a specific example of the This indicates a case where a 2-bit signals (m=1) are outputted as adjustment signals CAD 0> from the counter circuit 73A. In the oscillation circuit 72A, the test signal TS inputted from the external terminal T15A is inputted to an input terminal of the NAND gate as an enable signal. That is, the NAND gate is turned to logical inverting gate by the test signal TS and constitutes a ring oscillator together with an inverter gate array connected to the other input terminal.
[0081] The counter circuit 73A is a counter circuit in which flip-flop is cascade-connected. The oscillation signal CLK is inputted to a clock terminal (CLK) of the flip-flop of the lowest bit. Then, the adjustment signals CAD1:0> are outputted from each flip-flop. The adjustment signals CAD1:0> are supplied to the multiplexer 51 and at the same time to the memory circuit 42A.
[0082] The memory circuit 42A contains latch sec...
third embodiment
[0090] A circuit block diagram of the third embodiment for adjustment of the internal power source voltage VII shown in FIG. 12 indicates a case where the adjustment test of the internal power source voltage VII in the semiconductor integrated circuit device provided with a self-diagnosis test (BIST) circuit 81 is executed as a self-diagnosis test by BIST circuit 81.
[0091] Additionally, this block diagram shows a case where the predetermined signals MS0> are stored in a nonvolatile memory circuit 43. Because generally, data writing time to the nonvolatile memory circuit 43 is longer than increment period of the adjustment signal BAD0>, this embodiment includes a latch circuit 44 for temporarily holding the adjustment signals BAD0> to be stored. The adjustment signals BAD0> are held on the latch circuit 44 and written into the nonvolatile memory circuit 43.
[0092] The BIST circuit 81 starts the self-diagnosis test according to the test signal TS supplied from the external terminal T1...
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