Memory controller method and system compensating for memory cell data losses

Abstract

A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.

Description

TECHNICAL FIELD [0001] This invention relates to dynamic random access memory (“DRAM”) devices and controllers for such memory device, and, more particularly, to a method and system for controlling the operation of a memory controller, a memory module or a DRAM to manage the rate at which data bits stored in the DRAM are lost during refresh. BACKGROUND OF THE INVENTION [0002] As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power. [0003] Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends ...

AI Technical Summary

Benefits of technology

The patent describes a system and method for refreshing rows of dynamic random access memory cells to prevent data loss caused by errors in some of the cells. The system determines which rows of memory cells need to be refreshed based on their proximity to rows that have been identified as containing error-prone memory cells. The rows containing error-prone memory cells are refreshed at a faster rate to ensure that data stored in these cells is not lost. The system also detects and corrects data read errors by writing error correcting codes along with the data and processing them to identify and correct the errors. Overall, this technology helps to prevent data loss and improve the reliability of dynamic random access memory.

Problems solved by technology

The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged.

For example, electronic devices, such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power.

The power consumed by DRAM devices is also affected by their operating mode.

A DRAM, for example, will generally consume a relatively large amount of power when the memory cells of the DRAM are being refreshed.

A relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence.

As a result, DRAM refreshes tends to be particularly power-hungry operations.

Further, since refreshing memory cells must be accomplished even when the DRAM is not being used and is thus inactive, the amount of power consumed by refresh is a critical determinant of the amount of power consumed by the DRAM over an extended period.

However, reducing the refresh rate increases the risk of data stored in the DRAM memory cells being lost.

More specifically, since, as mentioned above, DRAM memory cells are essentially capacitors, charge inherently leaks from the memory cell capacitors, which can change the value of a data bit stored in the memory cell over time.

However, current leaks from capacitors at varying rates.

Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit.

On the other hand, current leaks from most DRAM memory cells at much slower rates that span a wide range.

However, the rate of current leakage from DRAM memory cells can change after production testing, both as a matter of time and from subsequent production steps, such as in packaging DRAM chips.

Current leakage, and hence the rate of data loss, can also be effected by environmental factors, such as the temperature of DRAM devices.

Therefore, despite production testing, a few memory cells will typically be unable to retain stored data bits at normal refresh rates.

However, the use of ECCs requires that a significant portion of the DRAM storage capacity be used to store the ECCs, thus effectively reducing the storage capacity of the DRAM.

Furthermore, the need to perform ECC processing on read data all during refresh can consume a significant amount of power.

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