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Charge trapping dielectric structure for non-volatile memory

Inactive Publication Date: 2006-06-01
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0037] While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

Problems solved by technology

One problem associated with charge trapping structures used in non-volatile memory is data retention.
However, leakage of trapped charge occurs in such devices due to defects in the materials which accumulate over long use, or which are inherent in the structures.

Method used

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  • Charge trapping dielectric structure for non-volatile memory
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  • Charge trapping dielectric structure for non-volatile memory

Examples

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Embodiment Construction

[0021] A detailed description of embodiments of the present invention is provided with reference to the FIGS. 1-9.

[0022]FIG. 1 is a simplified block diagram of an integrated circuit including charge storage memory cells. The integrated circuit includes a memory array 100 implemented using charge trapping memory cells having a charge trapping dielectric structure with an energy gap gradient. An alternative includes a floating gate memory cell with an interpoly dielectric structure including a middle dielectric layer with an energy gap gradient. The energy gap gradient establishes a weak electric field at equilibrium, opposing charge leakage, and improves charge retention and durability of the memory device. A page / row decoder 101 is coupled to a plurality of word lines 102 arranged along rows in the memory array 100. A column decoder 103 is coupled to a plurality of bit lines 104 arranged along columns in the memory array 100. Addresses are supplied on bus 105 to column decoder 103 ...

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Abstract

An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to charge trapping dielectric structures and to non-volatile memory based on such structures. [0003] 2. Description of Related Art [0004] Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As neg...

Claims

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Application Information

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IPC IPC(8): H01L29/792
CPCH01L29/513H01L29/7881H01L29/7923
Inventor WANG, SZU-YU
Owner MACRONIX INT CO LTD
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