Semiconductor device and method of manufacturing the same

Abstract

It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “−” functions as a gate electrode of an original MOS transistor.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the semiconductor device. [0003] 2. Description of the Background Art [0004] Attention has recently been paid to a semiconductor device referred to as an SOI (Silicon-On-Insulator) device to be a high-speed device having low power consumption. [0005] The SOI device is fabricated on an SOI substrate having an SOI structure in which a buried oxide film is interposed between an SOI layer and a silicon substrate. In particular, an SOI device in which an SOI layer to be an upper silicon layer has a small thickness (up to approximately several μm) is referred to as a thin film SOI device to which attention has been paid and has been expected for application to an LSI for mobile equipment. Conventionally, an SOI element (a (semiconductor) element formed on an SOI layer having an SOI structure) penetrates through Si...

AI Technical Summary

Benefits of technology

"The present invention relates to a semiconductor device with an SOI structure and a method of manufacturing the same. The invention aims to solve issues such as latch up free, resistance to noises, and the floating-body effect in a thin film SOI device. The invention provides a partial isolation and complete isolation combination technique that combines the advantages of both techniques. The invention also addresses the problem of varying isolation edges and body resistance in conventional devices. The invention provides a semiconductor device with an SOI structure that includes a MOS transistor with a body region potential setting portion to fix an electric potential and a method of manufacturing the same. The invention also provides a semiconductor device with an SOI structure that includes a body region potential setting portion and a gate extension region to electrically block the body region source / drain adjacent portion and the source and drain regions through the gate extension region. The technical effects of the invention include improved isolation and stability, reduced leakage current, and improved reliability of the device."

Problems solved by technology

The advantage is not always sufficient for a high breakdown voltage element or a device requiring high reliability of a hot carrier.

Consequently, the partial isolation technique has a technical background in which the reliability of a hot carrier and the frequency dependency of a delay time are not always sufficient.

The floating structure has a disadvantage in that a threshold voltage has a frequency dependency.

Moreover, a reduction in the body resistance can raise a drain breakdown voltage.

Furthermore, it is possible to prevent the reliability of the gate oxide film from being deteriorated due to the isolation edge.

However, there is a disadvantage that the pn junction capacitance is increased.

However, there is also a disadvantage that a threshold is varied due to a variation in a thickness of an SOI layer 4.

Consequently, there is a problem in that a gate oxide film provided under the H gate electrode 71 is greatly damaged during the ion implantation.

Moreover, there is a problem in that B, BF2 or the like implanted as the p-type impurity is diffused into a gate electrode region formed in an active region, resulting in a variation in a threshold voltage depending on a process temperature.

Therefore, it is possible to prevent the reliability of the gate oxide film in the isolation edge portion from being deteriorated.

In a transistor fabricated in the complete isolation region having the low isolation edge shape, moreover, there is a possibility that an increase in a leakage current generated by a local parasitic MOS might be caused by a drop in a threshold voltage due to a reduction in the thickness of the gate oxide film.

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