Precision low noise delta-sigma ADC with ac feed forward and merged coarse and fine results

Abstract

A delta-sigma converter has coarse and fine ADCs, wherein an integrated error signal is coupled to the coarse ADC whose output drives a DAC to create feedback that achieves loop balance. The coarse ADC provides the most significant bits of the result. The integrated error signal is also applied to a fine ADC whose output bits are not incorporated into the feedback, but which are combined with those of the coarse ADC and the combination applied to a filter that averages the hunting that represents loop balance. A DC feed forward circuit shunts the integrator with a replica of the applied input signal to apply it to the coarse ADC through a summer, allowing its output to be just the integrated error signal without including the applied input. If continuous integration is used, an AC feed forward circuit provides a compensatory voltage that is removed from the integrator output (or alternatively, is added to its input) and that corrects for a frequency dependent error.

Description

REFERENCE TO ISSUED PATENT [0001] The subject matter of U.S. Pat. No. 6,876,241 B2 issued 5 Apr. 2005 and entitled CIRCUIT FOR GENERATING FROM LOW VOLTAGE EDGES HIGHER PULSES HAVING PRECISE AMPLITUDES AND DURATIONS, filed 31 Jul. 2003 by William H. Coley and Stephen B. Venzke and assigned to Agilent Technologies, Inc., is of interest to the subject matter disclosed herein. In particular, it pertains to a preferred way of implementing the Feedback DAC for the delta-sigma architecture described in this Application. For this reason, and for the sake of brevity, CIRCUIT FOR GENERATING FROM LOW VOLTAGE EDGES HIGHER PULSES HAVING PRECISE AMPLITUDES AND DURATIONS is hereby expressly incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] The basic delta-sigma architecture is one where an analog input value is summed with a feedback value (which is often implemented as a voltage) to produce an error difference that is integrated and subsequently quantized into discrete values by...

AI Technical Summary

Benefits of technology

The patent describes a method for achieving high-speed and precise results using a delta-sigma converter. The method involves a coarse / fine architecture for two ADCs, an integrated error signal, and a feedback mechanism. The coarse ADC provides the most significant digits, while the fine ADC combines its output bits with those of the coarse ADC. The combined bits are then processed and applied to a filter that averages the hunting to achieve loop balance. This results in a significantly increased resolution of the converter and allows for variable speed-resolution selection. The overall linearity is dependent upon the precision of the DAC. A DC feed forward circuit removes the integrator output from the feedback mechanism, reducing the need for dynamic range of the fine ADC. An AC feed forward circuit corrects for frequency-related errors. The technique uses a minimum of components and is compatible with different integration techniques.

Problems solved by technology

However, such switched capacitor integration techniques are subject to various error mechanisms that limit the precision of the delta-sigma converters of which they are a part, even for DC inputs.

Unfortunately, the genuine analog integrator needed to obtain high precision for DC creates a frequency related error (in the integrated loop error signal) that increases as frequency gets higher, and degrades loop performance.

Thus, the use of a continuous integrator with an AC input is another area of delta-sigma behavior that is susceptible of improvement.

In one sense these additional movements in the error signal constitute unwanted components that adversely affect the output (they arise, as far as a quantized view of the loop's universe is concerned, ‘out of nowhere’).

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